Electronic musical instrument

ABSTRACT

A tone production assignment circuit produces control information representing assigned key code, key-on etc. Such information has a large number of bits with respect to each channel. A multiplexing circuit has output lines the number of which is smaller than the bit number of the information and divides the information with a plurality of time slots with respect to one channel. The multiplexing circuit is controlled by a signal from a timing signal generation circuit. The multiplexing circuit is capable of rearranging information for transmitting information required for the respective individual channels and also capable of inserting a timing data in an available time slot. A multiple data analysis circuit decodes the information provided by the multiplexing circuit. Tone generators are provided for the respective channels and each one of them functions to latch only corresponding information among the decoded information by a latch circuit.

BACKGROUND OF THE INVENTION

This invention relates to a compound tone type electronic musicalinstrument employing a tone production assignment circuit.

DESCRIPTION OF THE PRIOR ART

An electronic musical instrument is known in the art in which a toneselected by key depression is assigned to a suitable tone productionchannel by a tone tone production assignment circuit, and the tone isproduced by using the tone generator of that channel. In producing atone by using a tone generator, there are a number of pieces ofinformation as to the tone which should be supplied to the tonegenerator. In a device disclosed by the specification of U.S. Pat. No.3,882,751 entitled "Electronic Musical Instrument" or by thespecification of U.S. Pat. No. 4,114,495, entitled "Channel Processor",in addition to information (key code) representative of a key nameassigned to a relevant channel, information representative of thedepression of the key, information representative of the release of thekey, and clear information representative of the fact that theassignment to the channel has been cancelled are outputted by a toneproduction assignment circuit and are applied to a tone generator. Theinformation (key code) representative of a key name consists of a notecode representative of a note, an octave code representative of anoctave, and a keyboard code representative of a keyboard. If keydepression information and other control data are added to theaforementioned codes, data of the order of ten to fifteen bits isapplied to the tone generator section from the tone productionassignment section. In manufacturing the tone production assignmentsection and the tone generator section in the form of integratedcircuits, it is required to provide as many pins as the number of bitsof data used between the two sections. Therefore, as the number of bitsof data supplied to the tone generator section from the tone productionassignment circuit increases, the number of pins in the integratedcircuit is increased, which will be an obstacle to miniaturization ofthe sections.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an electronicmusical instrument including tone generators individually functioningfor each of tone production channels, in which the number of wiresbetween the tone production assignment circuit and the tone generatorsis remarkably reduced by supplying information concerning tones assignedto the respective channels to the tone generators in a time divisionmultiplexed form. It is another object of the invention to provide anelectronic musical instrument in which, in distributing the timedivision multiplexed information to the respective tone generators,timing for the distribution is determined by using single reference datarepresenting a reference timing in a time slot train and informationtransmitted from the tone production assignment circuit to the tonegenerators thereby is simplified.

These and other objects and features of the present invention willbecome apparent from the description made below in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram illustrating one example of an electronicmusical instrument according to this invention;

FIG. 2 is a diagram explaining a method of illustrating various circuitelements;

FIG. 3 is a timing chart of various signals employed for controlling avariety of circuits included in a channel processor shown in FIG. 1;

FIG. 4 is a block diagram illustrating a timing signal generatingcircuit in FIG. 1, in detail;

FIG. 5 is a detailed block diagram illustrating a key code memorycircuit, a key code comparison circuit and a data multiplex circuitshown in FIG. 1;

FIG. 6 is a block diagram illustrating an assignment control circuit andan attack system key-on signal generating circuit shown in FIG. 1, indetail;

FIG. 7 is also a block diagram illustrating a truncate circuit and anautomatic chord key-on signal generating circuit in FIG. 1 in detail;

FIG. 8 is a timing chart for a description of the operation of the datamultiplex circuit shown in FIG. 5;

FIG. 9 is a diagram for a description of the contents of data for everytime slot with respect to data KC₁ -KC₄ outputted by the data multiplexcircuit shown in FIG. 5;

FIG. 10 is a clock diagram showing one example of a digital tonegenerator shown in FIG. 1.

FIG. 11 is a block diagram illustrating a multiplex data analysiscircuit in FIG. 10 in detail;

FIG. 12 is a timing chart for a description of the operation of themultiplex data analysis circuit shown in FIG. 11;

FIG. 13 is a block diagram illustrating in detail the submultiplefrequency wave signal generator shown in FIG. 10;

FIG. 14 is a timing chart showing a state of submultiple frequency datagenerated in series by the submultiple frequency wave signal generator;

FIG. 15 is a circuit diagram illustrating in detail an example of theupper keyboard tone generator shown FIG. 10;

FIG. 16 is a circuit diagram illustrating in detail an example of eachof the lower keyboard tone generator and the automatic chord toneenvelope control section shown in FIG. 10; and

FIG. 17 is a circuit diagram showing the pedal keyboard tone generatorshown in FIG. 10.

DETAILED DESCRIPTION OF THE INVENTION Description of the generalarrangement of this invention

This invention will be described with reference to its preferredembodiment illustrated in the accompanying drawings.

Referring to FIG. 1, a keyboard section 10 comprises an upper keyboard,a lower keyboard, a pedal keyboard, and a variety of switches forcontrol. A key coder .Iadd.or key information generating means.Iaddend.11 operates to detect the on-off operations of the keys and theswitches in the key-board section 10, thereby to output pieces ofinformation representative of depressed keys and various pieces ofcontrol information. A channel processor 12 comprises a tone productionassignment circuit .Iadd.or channel assignment means .Iaddend.13, a datamultiplex circuit 14, and a timing signal generating circuit 15 for theabove-described assignment and multiplex. The tone production assignmentcircuit 13 is to assign a depressed key (or a tone to be produced) toany of a certain number (sixteen, for instance) of tone productionchannels, and the assignment is carried out in accordance withinformation (key code) representative of a depressed key from the keycoder 11. In this tone production assignment circuit 13, a key codememory circuit 17 has a certain number of memory positions, whichcorresponds to the number of tone production channels, the key codememory circuit 17 having a gate in its input side. As a result of anassignment operation, a key code N₁ -B₃ delivered from the key coder 11is stored in one of the memory positions in the key code memory circuit17. The fundamental conditions in the assignment operation of the toneproduction assigning circuit 13 are as follows:

(A) The assignment should be done for a memory position where no storageis made (or an empty channel), and

(B) A key code representative of the same key as a key (being depressed)whose tone is being produced should not be stored, in duplication, in aplurality of memory positions.

However, as far as the condition (B) concerns, in the case where thesame key code as an old key code (not used for tone production) which isstored in a channel which is not in tone production (not in keydepression) is newly supplied upon key depression, the new key code maybe assigned to a different channel. Such assignment control is effectedin the case of "key on again" described later.

A key code comparison circuit 18 operates to compare a key code N₁ -B₃applied thereto from the key coder 11 with an assigned key code N₁*-B₃ * which has been stored in the memory circuit 17, and it outputs acomparison output EQ depending on coincidence or non-coincidence. Anassignment control section 19 operates to detect whether the assignmentconditions such as the above-described conditions (A) and (B) aresatisfied or not. Upon satisfaction, the section 19 outputs a loadsignal LD which is applied to the key code memory circuit 17, thereby tocause the latter 17 to store an input key code N₁ -B₃. In addition, theassignment control section provides a key-on signal KO₁ or KO₂representative of the fact that a key assigned to a channel is beingdepressed.

An attack type key-on signal generating circuit 20 operates when anattack type envelope waveform is employed as a musical tone amplitudeenvelope, and the circuit 20 serves to reduce the generation time widthof the key-on signal KO₁ or KO₂ provided by the assignment controlsection 19 to a relatively short time width (of the order of 10 ms, forinstance). A truncate circuit 21 is to detect a channel to which a keywhich was released earliest is assigned, and the circuit 21 outputs atruncate channel designating signal TR in accordance with thisdetection. In the assignment control section 19, control is effected sothat the old assignment of a channel represented by the truncate channeldesignating signal TR is cancelled and that a key newly depressed isassigned to that channel.

A key-on signal generating circuit 22 for automatic chords (hereinafterreferred to as "an automatic chord key-on signal generating circuit 22"when applicable) outputs a key-on signal KO₃ in accordance with a signalCG representative of the tone production timing of an automatic chord.An automatic arpeggio circuit 23 detects successively the key codes N₁*-B₃ * which have been stored in the key code memory circuit 17 and, forinstance, concern the lower keyboard only, thereby to outputs the keycodes AN₁ -AB₂ of tones to be produced as automatic arpeggio tones. Thekey codes AN₁ -AB₂ of automatic arpeggio tones are inputted in anarpeggio-only-channel of the key code memory circuit under the controlof the assignment control section 19.

The timing signal generating circuit 15 outputs a timing signal forcontrolling the tone production assignment of the tone productionassignment circuit 13, and a timing signal for controlling the timedivision multiplex operation of various pieces of information in thedata multiplex circuit 14. The data multiplex circuit 14 multiplexesassigned key information (such as the key code N₁ *-B₃ *, and the key-onsignals KO₁, KO₂ and KO₃) applied thereto from the tone productionassignment circuit 13 and control information from the key coder 11 (orother relevant switches) into time division multiplexed data inaccordance with the timing signal applied thereto from the timing signalgenerating circuit 15. Key information or control information of a largenumber of bits inputted into the data multiplex circuit 14 ismultiplexed into data of a smaller number of bits (for instance, it isoutputted as four-bit data KC₁, KC₂, KC₃ and KC₄). The multiplex dataKC₁, KD₂, KC₃ and KC₄ outputted by the data multiplex circuit 14 aredelivered, as the output of the channel processor 12, to a digital tonegenerator section 16. In the digital tone generator section 16, variouspieces of information (such as the key codes N₁ *-B₃ *, the key-onsignals KO₁, KO₂ and KO₃, and the control information) are restored fromthe multiplex data KC₁, KC₂, KC₃ and KC₄ thus delivered, separatelyaccording to the tone production channels, and in accordance with thesepieces of information musical tone signals are provided separatelyaccording to the channels. The digital tone generator section 16comprises a tone generator of the type that musical tone signals havingtone pitches corresponding to digital information can be produced inaccordance with the digital information. In the example shown in FIG. 1,the key coder 11 and the channel processor 12 is in the form of one chipof integrated circuit, while the digital tone generator section 16 is inthe form of another chip of integrated circuit.

Detailed description of the constructions and operations of varioussections

(1) Explanation of a Method of Illustrating Various Circuit Elements inthe Accompanying Drawings, and Timing Signals:

FIG. 2 shows one example of a method of illustrating various circuitelements in the accompanying drawings. In FIG. 2, the part (a) shows amultiple-input type AND circuit; the part (b), a multiple-input type ORcircuit; the part (c), a delay flip-flop, and the part (d), a shiftregister. In a multiple-input type logical circuit element (the part (a)or (b) in FIG. 2), one input line is provided on the input side of thecircuit, a plurality of signal lines are intersected with the inputline, and the point of intersection of a signal line for a signal to beinputted to the circuit and the input line is encircled. Accordingly,the logical expression of the part (a) of FIG. 2 is Q=A·B·D, while thelogical expression of the part (b) of FIG. 2 is Q=A+B+C. The digit "1"in the block indicating a delay flip-flop, as shown in the part (c) ofFIG. 2, is intended to mean that input data is delayed by one bit time(one stage). In the part (d) of FIG. 2, the numerator of a fractionindicates the number of all stages in the shift register, while thedenominator indicates the bit number of a stage. Where no clock pulse isindicated for a delay flip-flop or a shift register in a drawing, itshould be understood that it is driven by a main clock pulse φ₁ (whichis, for instance, a two-phase clock pulse having a period of 1 μs).Where an output is led out of a stage in a shift register, the stage'sorder is indicated by a number in the block, from which an output lineis extended.

In the tone production assignment circuit 13, the tone productionchannels are formed in time division manner. The time-division timeslots of the channels are segregated successively with the timing of themain clock pulse φ₁. In this example, the period of the main clock pulseφ₁ is one μs. The part (a) of FIG. 3 shows the channel time slots(channel times) in the tone production assignment circuit 13, andsixteen time slots each having a time width of 1 μs correspond the firstthrough sixteenth channels, respectively.

In this example, the tone production channels are determined separatelyaccording to the keyboards, and the tone production assignment circuit13 operates to assign key depression tones of relevant keyboards to anyof the tone production channels thus determined. For instance, the upperkeyboard tones are assigned to the third, fourth, sixth, seventh, tenth,thirteenth and sixteenth channels, while the lower keyboard tones areassigned to the second, fifth, eighth, ninth, eleventh, twelfth andfifteenth channels. The pedal keyboard tones are assigned to the firstchannel. The fourteenth channel is used for assigning the automaticarpeggio tones. Signals representative of the channels classifiedseparately according to the keyboards and the functions as describedabove are outputted by the timing signal generating circuit 15.

(2) Description of the Timing Signal Generating Circuit 15:

Shown in FIG. 4 is a detailed example of the timing signal generatingcircuit 15. A counter 24 comprising four 1/2 frequency divisionflip-flops cascade-connected subjects the main clock pulse φ₁ to 1/16frequency division. This counter 24 is reset by an initial clear signalIC when the power switch is turned on, and thereafter it successivelycounts DC signals "1" applied to its count input terminal, with thetiming of the main clock pulse φ₁ (not shown). When the count value ofthe counter 24 reaches "1 1 1 1", an AND circuit 25 is operated tooutput a signal "1" having a time width of 1 μs. Thus, the AND circuit25 outputs the signal "1" every 16 μs, and this output corresponds tothe 16th channel time. The output of the AND circuit 25 is inputted intoa 16-stage/1-bit shift register 26, where it is successively shiftedaccording to the main clock pulse φ₁ (not shown). Accordingly, a singlesignal "1" is held in the shift register 26, and this signal "1" issuccessively shifted toward the 16th stage from the first stage, as aresult of which the channel time in time division manner as indicated inthe part (a) of FIG. 3 is formed. The outputs of the 3rd, 4th, 6th, 7th,10th and 13th stages in the shift register 26 are applied to an ORcircuit 27, the output of which is used as an upper-keyboard-onlychannel signal YUK. Similarly, the outputs of the 2nd, 5th, 8th, 9th,11th, 12th and 15th stages in the shift register 26 are applied to an ORcircuit 28, the output of which is used as a lower-keyboard-only channelsignal YLK. The output of the 1st stage in the shift register 26 is usedas a pedal-keyboard-only channel signal YPK. In addition, the output ofthe 14th stage in the shift register 26 is used as anautomatic-arpeggio-only signal YAR. The generation of these channelssignals YUK, YLK, YPK and YAR are as indicated in the parts (b) through(e) of FIG. 3, respectively.

One cycle of processing operation in the channel processor 12 isaccomplished in three circulations (48 μs) of the time division channeltime. A signal H1 indicated in the part (f) of FIG. 3 shows the first 16μs period (the first processing period) of one operation cycle taking 48μs; a signal H2 indicated in the part (g) of FIG. 3 shows the second 16μs period (the second processing period); and a signal H3 in the part(h) shows the last 16 μs period (the third processing period). Afrequency division signal having a period of 16 μs outputted by thecounter 24 in FIG. 4 is inputted to a 1/3 frequency division circuit 29,from which a 2-bit output which is changed in three ways "0 0", "0 1"and "1 0" at the time intervals of 16 μs and repeats this change every48 μs is obtained. This output of the 1/3 frequency division circuit 29is applied to a decoder 30, where the first, second and third processingperiod signals H1, H2 and H3 are obtained in correspondence to theoutputs "0 0", "0 1" and "1 0", respectively.

The timing signal generating circuit 15 generates twophase clock pulsesφ_(A), and φ_(B) each having a period of 48 μs as indicated in the parts(i) and (j) of FIG. 3, in accordance with the processing period signalsH1, H2 and H3 and the contents of the shift register 26. The two-phaseclock pulses φ_(A) and φ_(B) are used in the key coder 11 so as todeliver various data out of the latter 11 in synchronization with theperiod of 48 μs of each of the first, second and third processing periodsignals H1, H2 and H3.

(3) Description of the Key Coder 11

A key coder of the type that is disclosed by the specification of U.S.Pat. No. 4,114,495 may be preferably employed as the key coder 11. Thekey coder 11 operates to output key codes N₁ -B₃ representative of keysdepressed in the keyboard section 10. The key codes N₁ -B₃ are outputtedin time division manner at predetermined time intervals when the keysare depressed. This time interval is controlled by the aforementionedclock pulses φ_(A) and φ_(B) so as to have a time width of 48 μs insynchronization with the period of time from the rise of the pulse φ_(A)to the fall of the pulse φ_(B). For example, if the key code N₁ -B₃ of adepressed key is applied to the channel processor 12 from the key coder11 with the time width of 48 μs equal to the period of time from therise of a clock pulse φ_(A) to a clock pulse φ_(B), then the key code N₁-B₃ of another depressed key is applied thereto in the period of time of48 μs from the rise of the following clock pulse φ_(A) to the fall ofthe following clock φ_(B). The time width for delivering one key code N₁-B₃ from the key coder 11 is as indicated in the part (k) of FIG. 3.

The key code N₁ -B₃ is a 7-bit data consisting of a note code N₁, N₂,N₃, N₄ representative of a note and a block code B₁, B₂, B₃representative of an octave range. One example of the relations betweenthe contents of note codes N₁ -N₄ and notes is indicated in Table 1below:

                  TABLE 1                                                         ______________________________________                                        Note   N.sub.4  N.sub.3                                                                             N.sub.2                                                                              N.sub.1                                                                           Decimal notation                             ______________________________________                                        C♯                                                                       0        0     0      1   1                                            C      0        0     1      0   2                                            D♯                                                                       0        0     1      1   3                                            E      0        1     0      1   5                                            F      0        1     1      0   6                                            F♯                                                                       0        1     1      1   7                                            G      1        0     0      1   9                                            G♯                                                                       1        0     1      0   10                                           A      1        0     1      1   11                                           A♯                                                                       1        1     0      1   13                                           B      1        1     1      0   14                                           C      1        1     0      0   12                                           ______________________________________                                    

In Table 1, the note code N₄ -N₁ of note C is "1 1 0 0" (decimal number12); however, it is converted into "1 1 1 1" (decimal number 15) when itis practically used for musical tone production. The reason for this isthat a reference data used for restoring multiplexed data is provided bythe data multiplex circuit 14 so that it has a content "1 1 1 1", andaccordingly it is necessary to avoid the duplication with this.

The relation-ships between the contents of block codes B₁ -B₃ and octaveranges are indicated in Table 2 by way of example:

                  TABLE 2                                                         ______________________________________                                               Octave Range                                                                            Upper  Lower    Pedal                                        B.sub.3                                                                           B.sub.2                                                                             B.sub.1                                                                              keyboard                                                                             keyboard keyboard                                                                             Arpeggio                              ______________________________________                                        0   0     0      C.sub.3                                                                              C.sub.2  C.sub.1                                      0   0     1      C.sub.3.sup.♯  ˜ C.sub.4                                           C.sub.2.sup.♯  ˜ C.sub.3                                             C.sub.1.sup.♯  ˜                                            C.sub.2                                                                              C.sub.2.sup.♯                                                     ˜ C.sub.3                       0   1     0      C.sub.4.sup.♯  ˜ C.sub.5                                           C.sub.3.sup.♯  ˜ C.sub.4                                             C.sub.2.sup.♯  ˜                                            C.sub.3                                                                              C.sub.3.sup.♯                                                     ˜ C.sub.4                       0   1     1      C.sub.5.sup.♯  ˜ C.sub.6                                           C.sub.4.sup.♯  ˜ C.sub.5                                                    C.sub.4.sup.♯                                                     ˜ C.sub.5                       1   0     0      C.sub.6.sup.♯  ˜ C.sub.7                                           C.sub.5.sup.♯  ˜ C.sub.6                                                    C.sub.5.sup.♯                                                     ˜ C.sub.6                       ______________________________________                                    

As is clear from Table 2, the relationships between block codes B₁ -B₃and octave ranges are different from one another separately according tothe kinds of keyboard. For instance, the key range of the upper keyboardis from note C₃ to note C₇, that is, notes lower in tone pitch than noteC₃ (exclusive) (notes lower than note B₂ (inclusive)) and note higher intone pitch than note C₇ (exclusive) (note higher than note C₇ ♯(inclusive)) are not used, and even with the same block code B₁ -B₃ theoctave range of the upper keyboard is different by one octave from thatof the lower keyboard. In addition, the octave range to which one andthe same block code B₁ -B₃ is not an ordinary range of from note C tonote B, but a range of from note C♯ to note C on the higher tone side.Accordingly, the block code B₁ -B₃ "0 0 0" in the lowest range isapplied only to one tone C which is the lowest. Indicated in the column"Arpeggio" in Table 2 are tone range corresponding to the contents ofthe block code AB₁, AB₂ included in a key code AN₁ -AB₂ for automaticarpeggio tone which is provided by the automatic arpeggio circuit 23(FIG. 1). The tone ranges are substantially equal to those for the blockcodes B₁ -B₃ for the lower keyboard; however, it should be noted thatnote C₂ in the lowest tone range is not used in the automatic arpeggio.Accordingly, with respect to the block code AB₁, AB₂ for arpeggio, a bitcorresponding the third bit B₃ is not required. The key range of thepedal keyboard is from note C₁ to note C₃, and therefore in this casealso the data of the third bit B₃ is unnecessary.

Keyboard signals U, L, and P representative of keyboards to which keysrepresented by key codes N₁ -B₃ belong are outputted by the key coder 11in synchronization with the key codes N₁ -B₃ and with a time width of 48μs. The signals U, L and P represent the upper keyboard, the lowerkeyboard and the pedal keyboard, respectively.

A depressed key's key code N₁ -B₃ and its keyboard signal U, L or P areprovided by the key coder 11 repeatedly at suitable time intervals. Uponrelease of the key, provision of the key code N₁ -B₃ is suspended. Inorder to detect what key code concerns the released key among the keycodes which have been provided, the key coder 11 periodically generatesa key-off detecting signal X. The generation timing of the key-offdetecting signal X is 48 μs equal to one key code delivery timeindicated in the part (k) of FIG. 3. While this key-off detecting signalX is being produced, none of the key code N₁ -B₃ and the keyboardsignals U, L and P are produced. The generation interval of the key-offdetecting signal X is of the order of 5 ms for instance. It is arelatively long period of time for a digital system, but it is so shortfor a person's hearing sense that he cannot distinguish two successivelyproduced key-off detecting signals X. The assignment control section 19in the tone production assignment circuit section 13, under theconditions that no key code N₁ -B₃ is supplied to the channel processor12 during one generation interval of key-off detecting signal X althoughit has been supplied to the channel processor 12, determines that thekey concerning the key code N₁ -B₃ has been released.

In this example, the key coder 11 is so designed that it delivers notonly information (N₁ -B₃, U, L, P and X) concerning keys as wasdescribed above but also data selected by switches employed for musicaltone control or function selection. When automatic arpeggio performanceis selected, the key coder 11 outputs an automatic arpeggio selectionsignal ARP with a time width of 48 μs synchronous with one key codedelivery time shown in the part (k) of FIG. 3. Furthermore, the keycoder 11 is so designed that when the automatic arpeggio selectionsignal ARP is outputted, pieces of information (N₁ -B₃, U, L P and X)concerning keys are not outputted thereby. The key coder 11 outputs anenvelope control signal EC. This signal EC is to change a producedtone's amplitude envelope waveform over to either a sustain tone systemenvelope waveform or an attack system envelope waveform, and has a DC"1" level or a DC "0" level according to the set positions of anenvelope control switch .[.(not shown).]. .Iadd.S_(EC) (FIG.1).Iaddend.. A damper signal DU outputted by the key coder is toabruptly eliminate a musical tone envelope waveform which remains as adecayed waveform even after key release, and has a DC "1" level or a DC"0" level according to the on-off operation of a damper switch .[.(notshown).]. .Iadd.S_(DU) (FIG. 1). Thus the key coder 11 includes meansfor generating envelope information (e.g., the signals EC and DU) todetermine the envelope characteristics of a tone.Iaddend..

Furthermore, the key coder 11 is so designed that process for automaticbass chord performance can be effected. That is, in the case where aautomatic bass chord performance is selected, an automatic bass's keycode N₁ -B₃ and an automatic chord's key code N₁ -B₃ are provided withsuitable timing in accordance with keys depressed in the keyboardsection 10. In an automatic bass chord performance, an automatic basschord selection signal ABC is outputted, in a direct current mode, bythe key coder 11. A slow rock selection signal SR has a DC "1" levelwhen a slow rock rhythm is selected. A chord timing signal CG isoutputted by the key coder 11 with the timing of producing an automaticchord. These signals ABC, SR and CG are applied through the channelprocessor 12 to the digital tone generator, where they are used tocontrol an automatic chord's amplitude envelope waveform.

In the "automatic bass chord performance", in general, keys in thekeyboard section are depressed in chord form, a chord name is detectedfrom the combination of the keys thus depressed, tones corresponding tothe root (fundamental note) and sub-notes of the chord are automaticallyproduced as bass tones in accordance with a bass pattern, and chordforming tones are produced automatically with chord tone producingtiming. A bass automatically formed in supplied, as a pedal keyboard keycode, to the channel processor 12, while a chord is supplied, as a lowerkeyboard key code, to the channel processor 12. In the electronicmusical instrument relating to this embodiment a device disclosed in thespecification entitled as "Musical Instrument with Automatic Bass Chordperformance Device" of U.S. patent application Ser. No. 825,443 filedAug. 17, 1977 and assigned to the same assignee as the present case, canbe employed for automatic bass chord performance. Such an "automaticbass chord performance control device" is provided on the output side ofthe key coder 11, that is, it is provided between the key coder 11 andthe channel processor 12. However, it should be noted that the"automatic bass chord performance control device" is included in the keycoder 11 in FIG. 1. In fact, it is possible that by following theteaching of the U.S. patent application Ser. No. 825,443 an automaticbass chord performance function can be incorporated in the key coder 11to commonly use the circuits. Accordingly, this embodiment may employ anarrangement in which an automatic bass chord performance function ispositively incorporated in the key coder 11, or it may employ anarrangement in which an original key coder part and an automatic basschord performance control part are segregated from each other in the keycoder 11 which is illustrated as one block for convenience indescription. The detailed description of the automatic bass chordperformance control will be omitted.

In addition, the key coder 11 outputs a memory signal MM representativeof the fact that information representative of a key depressed should bestored even after the release of the key so as to be used for musicaltone production, an up/turn selection signal UT for selecting anautomatic arpeggio tone's tone pitch increment pattern or increment anddecrement repetition pattern, and arpeggio pattern selection signalsAP₁, AP₂, AP₃ and AP₄ when required; however, their detaileddescriptions will be omitted.

(4) Description of the Tone Production Assigning Circuit Section 13:

One example of the tone production assignment circuit 13 will bedescribed in detail. Referring to FIG. 5, the key code memory circuit 17comprises a 16-stage/1-bit shift register 31, a data inputting ANDcircuit 32, a self-holding AND circuit 33 and an OR circuit 34 forsupplying input data to the first stage of the shift register 31 foreach bit of the key code N₁ -B₃. Each shift register 31 carries out itsshifting operation every 1 μs in accordance with the main clock pulseφ₁. The number of stages in the shift register 31 corresponds to thenumber of tone production channels. The key codes N₁ *-B₃ * of tonesassigned to the respective channels are stored in time division mannerin the stages of the shift registers 31. These key codes N₁ *-B₃ * aresuccessively outputted by the key code memory circuit 17 insynchronization with the respective channel times, each having 1 μs asindicated in the part (a) of FIG. 3, and are applied to the one inputside of a digital comparator 35 in a key code comparison circuit 18, tothe other input side of which the key code N₁ -B₃ having a time width of48 μs delivered from the key coder 11 is applied through a group of ORcircuits 36.

In the digital comparator 35, the key code N₁ -B₃ of a depressed keywhich is not changed for 48 μs is compared with the key code N₁ *-B₃which is changed every 1 μs and has been assigned already. In the casewhere the same key code N₁ -B₃ as the key code N₁ -B₃ has been stored inthe memory circuit 17, the coincidence detection signal EQ₁ is raised toa logical level "1" (hereinafter referred to as "1" when applicable) insynchronization with the channel time thereof. In the digital comparator35, the comparison is carried out independently of the keyboard of thekey code N₁ -B₃, and the coincidence detection signal EQ₁ is produced.The coincidence detection signal EQ₁ is applied to AND circuit 37, 38and 39, whereby only the coincidence detection signal EQ₁ which isprovided in the channel time of the same keyboard as a keyboard to whicha key code N₁ -B₃ supplied from the key coder 11 belongs is selected.For this purpose, the upper keyboard signal U or the lower keyboardsignal L or the pedal keyboard signal P delivered from the key coder 11in synchronization with a key code N₁ -B₃ is applied to the AND circuit37 or 38 or 39, respectively. A key code N₁ *-B₃ is assigned to thespecial channel for the respective keyboard, and therefore the signalsYUK, YLK and YPK representative of the special channels of thekeyboards, as indicated in the parts (b), (c) and (d) of FIG. 3 areapplied to the AND circuits 37, 38 and 39. The outputs of the ANDcircuits 37, 38 and 39 are applied to an OR circuit 40, the output ofwhich is applied, as a comparison output EQ, through an AND circuit 41and a line 42 to AND circuits 43 and 44 in the assignment controlsection 19 (FIG. 6). The AND circuit 41 is to suspend the application ofthe comparison output EQ to the assignment control circuit 19 while theautomatic arpeggio selection signal ARP is supplied thereto. In thiscase, the signal ARP is applied through an inverter 45 to the ANDcircuit 41 to disable the latter 41. As was described before, while theautomatic arpeggio selection signal ARP is being provided, none of thekeyboard signals U, L and P are provided. Therefore, the output of theOR circuit may be introduced to the line 42 without providing the ANDcircuit 41. For the period of 48 μs during which the automatic arpeggioselection signal ARP is outputted, the key code AN₁ -AB₂ of an automaticarpeggio tone is applied to the OR circuits 36 by the automatic arpeggiocircuit 23 (FIG. 1) and is stored in the key code memory circuit 17 withthe timing corresponding to the fourteenth channel which is the arpeggiospecial channel. The note code N₁ *-N₄ * of the output of the key codememory circuit 17 is supplied to the automatic arpeggio circuit 23 (FIG.1).

Referring to FIG. 6, the assignment control section 19 comprises akey-on memory 46, a lower keyboard key-on memory 47, a key-on temporarymemory, a key-off memory 49, and a circuit for controlling the datainputting operations and storage cancelling operations of thesememories. Each of the memories 46 through 49 has a 16-stage/1-bit shiftregister so as to store the data of the channels in time divisionmanner. When a key concerning a key code N₁ *-B₃ * which has beenassigned and stored in the key code memory circuit 17 is beingdepressed, a signal "1" (key-on signal KO) is stored by the key-onmemory 46 in synchronization with the relevant assigned channel.Accordingly, this indicates that tone assignment has already been doneto the channel for which the output of the key-on memory is at "1", andthe key of the tone is being depressed. .Iadd.Thus the key code memorycircuit 17 and the key-on memory 46 together comprise a memory means orassignment memory means storing for each assigned channel both a keycode and the associated key depression state data. .Iaddend.Theaforementioned comparison output EQ, the output KO of the key-on memory46 and a key code detecting signal KON from an OR circuit 50 (FIG. 5)are applied to the AND circuit 43. A note code N₁ -N₄ supplied by thekey coder 11 (or the note code AN₁ -AN₄ of an automatic arpeggio) isinputted to the 4-input OR circuit 50. Accordingly, when any key code N₁-B₃ is supplied to the key code memory circuit 17, the key codedetection signal KON is raised to "1".

Accordingly, the AND circuit 43 outputs a signal "1", when the followingthree conditions are satisfied:

(1) At present, a key code N₁ -B₃ (or AN₁ -AB₂) is supplied (KON="1").

(2) The key code N₁ -B₃ has already been assigned to a channel.(EQ="1").

(3) The tone assigned to the channel is of a key being depressed, (theoutput of the key-on memory 46 being at "1"). This output "1" of the ANDcircuit 43 will be referred to as "an assigned key-on signal AKON" whenapplicable. The signal AKON is applied through an OR circuit 51 and anAND circuit 52 to a delay flip-flop 53, where it is stored. This storageis self-maintained through the OR circuit 51 and the AND circuit 52. Asignal Y48 applied to the other input terminal of the is obtained byinverting a one cycle finish signal Y48 (the part (1) of FIG. 3). Morespecifically, the one cycle finish signal Y48 is provided by an ANDcircuit 54 in the timing signal generating circuit 15 (FIG. 4). Thethird process period signal H3 from the decoder 30 (the part (h) of FIG.3) and a pulse synchronous with the 16th channel time from the ANDcircuit 25 are applied to the AND circuit 54, and the one cycle finishsignal Y48 is provided in the last channel time of the process operationcycle as indicated in the part (1) of FIG. 3. Since the signal Y48 isobtained by inverting the output of the AND circuit 54 by means of aninverter 55, it is maintained at "1" for the period of 47 bit-timescovering the first and second process periods (H1 and H2) plus theperiod from the beginning of the third process period (H3) to the 15thbit-time thereof (cf. the part (m) of FIG. 3). The AND circuit 52 (FIG.6) enabled by the signal Y48 is disabled with the generation timing ofthe one cycle finish signal Y48. Therefore, the self-holding of thedelay flip-flop 53 is cleared at the last channel time of the thirdprocess period (H3).

In the case where a key code N₁ -B₃ supplied by the key coder 11 is onewhich has been assigned already, an assigned key-on signal AKON isprovided in a relevant assigned channel time of the 16 bit-times duringwhich the first process period signal H1 is outputted. Since this signalAKON is immediately stored in the delay flip-flop 53, the output of thedelay flip-flop 53 is maintained at "1" for the period of 16 bit-timeduring which the second process period signal H2 is ouputted. Thisoutput "1" of the delay flip-flop 53 is applied to an inverter 56, whereit's level is switched to a logical "0" level (hereinafter referred tomerely as "0" when applicable), as a result of which no new assignmentin the second process period (H2) is effected.

In contrast, in the case where a key code N₁ -B₃ supplied by the keycoder 11 has not been assigned yet (or in the case where an automaticarpeggio key code (AN₁ -AB₂ is supplied), the output of the AND circuit43 is always at "0" while the first and second process period signals H1and H2 are outputted. Accordingly, no signal "1" is stored in the delayflip-flop 53, and the output of the flip-flop 53 is maintained at "0".In this case, while the second process period signal H2 is provided, theoutput of the inverter 56 is at "1" without fail. This output "1" of theinverter 56 is applied through an OR circuit 57 to an AND circuit 58, asa result of which a new key-on signal NKO is provided which indicatesthe fact that a key is newly depressed. A key code detection signal KONis applied to the AND circuit 58 by the OR circuit 50 in FIG. 5. Whenthe output of the inverter 56 is at "1" and this key code detectionsignal KON is at "1" also, it means that a new key code N₁ -B₃ which isnot assigned yet is supplied. Such a new key code N₁ -B₃ should beassigned to any of the channels. For this purpose, the output of thekey-on memory 46 is applied through an inverter 57 to the AND circuit58, thereby to enable the AND circuit 58 in a channel time during whichkey release is effected, and to provide the new key-on signal NKO inthat channel time.

The new key-on signal NKO outputted by the AND circuit 58 is applied toAND circuits 60, 61, 62 and 63, and it is selected by one of the ANDcircuits 60 through 63 in synchronization with a single channel time.The new key-on signal NKO thus selected is applied through OR circuits64 and 65 to the key-on memory 46, where it is stored. The output "1" ofthe OR circuit 64 becomes a load signal LD. The upper keyboard signal U,the lower keyboard signal L, the pedal keyboard signal P and theautomatic arpeggio selection signal ARP are applied to the AND circuits60 through 63 by the key coder 11, respectively, as a result of whichone of the AND circuits 60 through 73, which corresponds to thekeyboards (or function) to which the key code N₁ -B₃ being suppliedbelongs, is enabled. Signals YUK2, YLK2, YPK2 and YAR2 representative ofthe keyboards and automatic arpeggio exclusive assignment channels areapplied to the AND circuits 60 through 63, respectively. These signalsYUK2, YLK2, YPK2 and YAR2 are the exclusive channel signals YUK, YLK,YPK and YAR (the parts (b) through (e) of FIG. 3) which occur during thesecond process period indicated in the part (g) of FIG. 3, and thesesignals are provided by AND circuits 66 through 69 in FIG. 4. The secondprocess period signal H2 is applied to one input terminal of each of theAND circuits 66 through 69 by the decoder 30, while the upper keyboardexclusive channel signal YUK, the lower keyboard exclusive channelsignal YLK, the pedal keyboard exclusive channel signal YPK and theautomatic arpeggio exclusive channel signal YAR are applied to theremaining input terminals of the AND circuits 66 through 69 by the ORcircuits 27, 28, 70 and 71, respectively. Thus, the signals YUK2, YLK2,YPK2 and YAR2 are provided in the exclusive channel times of the secondprocess period, respectively.

Each of the exclusive channels of the pedal keyboard tone and theautomatic arpeggio tone is one channel. Therefore, if the new key-onsignal NKO is provided while the pedal keyboard signal P or theautomatic arpeggio selection signal is being supplied, the AND circuit62 or 63 outputs a signal "1" in the first or fourteenth channel time ofthe second process period in response to the signal YPK2 or YAR2. Eachof the upper keyboard tone and the lower keyboard tone has sevenchannels as its exclusive channel. Therefore, in order to assign the newkey-on signal NKO to a single channel, a truncate channel designationsignal TR is employed. The signal TR is outputted by the truncatecircuit 21 (FIG. 7) as described later. The truncate channel designationsignal TR is provided in synchronization with the assignment channeltime of the key which has been released earliest in the upper keyboardand the assignment channel time of the key which has been releasedearliest in the lower keyboard, with respect to the tones beingsubjected to assignment. The signal TR thus provided is applied to ANDcircuits 72 and 73, where it is divided into an upper keyboard truncatechannel designation signal TRU and a lower keyboard truncate channeldesignation signal TRL separately according to the upper keyboardexclusive channel signal YUK and the lower keyboard exclusive channelsignal YLK. The signals TRU and TRL are applied to the AND circuits 60and 61, respectively, whereby the new key-on signal NKO is selected in asingle channel time of a relevant keyboard. When a signal "1" isoutputted by the AND circuit 60 or 61 once, the signal "1" is appliedthrough an OR circuit 74 or 75 and an AND circuit 76 or 76 to a delayflip-flop 78 or 79, where it is stored. This storage is self-held by thesignal Y48 applied to the AND circuit 76 or 76 until the one cyclefinish signal Y48 is provided. The output "1" of the delay flip-flop 78or 79 is applied through an inverter to the AND circuit 72 or 73 todisable the latter. Accordingly, even if the truncate channeldesignation signal TR is provided twice or more in different channelsrelating to one and the same keyboard, the truncate channel designationsignal TRU or TRL of the upper keyboard or the lower keyboard isgenerated only once in the second process period (the part (g) of FIG.3).

When any of the AND circuits 60 through 63 provides the output "1", anew assignment is carried out. More specifically, The signal "1"outputted by any of the AND circuits 60 through 63 in a single channeltime of the second process period is applied, as a load signal LD,through an OR circuit 64 to the key code memory circuit 17 (FIG. 5).Referring to FIG. 5, the load signal LD enables data inputting ANDcircuits 32 provided respectively for the bits in the key code memorycircuit 17. The load signal LD is further applied through a NOR circuit80 to self-holding AND circuits 33 to disable the latter. Therefore, thestored key code N₁ *-B₃ * of a channel for which the load signal LD isprovided is cleared, and a new key code N₁ -B₃ (or AN₁ -AB₂) is storedin the key code memory circuit 17 in synchronization with the relevantchannel time.

Referring back to FIG. 6, the output "1" of the OR circuit 64 is appliedthrough an OR circuit 65 to the key-on memory 46, whereby the key-onsignal KO is stored in synchronization with the storage of the new keycode N₁ -B₃ in the key code memory circuit 17. The output KO of thekey-on memory 46 is self-held by means of the OR circuit 65 and an ANDcircuit 81. The AND circuit 81 is disabled in the time of the channel towhich a key code N₁ *-B₃ * relating to key release has been assigned, asdescribed later.

The output of the OR circuit 65 is applied through a line 82 to an ANDcircuit 83. Accordingly, when a signal "1" representative of a key beingdepressed is inputted to the key-on memory 46, the AND circuit 83 isdisabled. Applied to the other input terminal of the AND circuit 83 is alower keyboard new key-on signal LNK representing the fact that a key isnewly depressed in the lower keyboard. The aforementioned output of theOR circuit 57 and the key code detection signal KON are applied to anAND circuit 84, and the lower keyboard signal L and the lower keyboardexclusive channel signal YLK 2 in the second process period are appliedto the remaining input terminals of the AND circuit 84. Accordingly, ifa key is depressed in the lower keyboard, at the beginning of thedepression the output LNK of the AND circuit 84 is raised to "1" onlyonce in synchronization with the lower keyboard exclusive channel timeof the second process period. In this operation, the OR circuit 65outputs a signal "1" in synchronization with the assignment channel ofthe tone of a key being depressed in the lower keyboard. Therefore, theoutput of the AND circuit 83 is raised to "1" in synchronization withthe assignment channel of the tone of the key being depressed in thelower keyboard. This output "1" is applied through an OR circuit 85 tothe lower keyboard key-on memory 47 where it is stored. This storage inthe memory 47 is self-held by means of the AND circuit 86 and the ORcircuit 85. The output of the NOR circuit 87 is applied to the ANDcircuit 86. The AND circuit is disabled when the initial clear signal Icis provided, in channel times other than the lower keyboard exclusivechannel (the signal YLK being at "1") or when the AND circuit 84provides the lower keyboard new key-on signal LNK. Applied through aline 166 to the other input terminal of the AND circuit 86 is a lowerkeyboard key depression memory signal LKM whose level is maintainedraised to "1" when a key is depressed in the lower keyboard. Therefore,when a key is depressed in the lower keyboard, the self-holding of thelower keyboard key-on memory 47 is permitted. A lower keyboard key-onsignal LKO is outputted by the lower keyboard key-on memory 47 in timedivision manner in synchronization with the channel time to which thetone of a key being depressed in the lower keyboard is assigned. Thissignal LKO is utilized in the automatic arpeggio circuit 23 (FIG. 1);however, its detailed description will be omitted.

(KEY-OFF DETECTION)

The load signal LD representing a channel to which a newly depressed keyis to be assigned is applied from the OR circuit 64 through a line 88(FIG. 6) to an OR circuit 89, and it is stored in the key-on temporarymemory 48. The key-on temporary memory 48 operates in such a mannerthat, if a key is depressed even once in one generation period of thekey-off inspection signal X, the memory 48 stores a signal "1" in theassignment channel of the key. This storage is self-held by means of anAND circuit 90. Upon application of the key-off inspection signal X bythe key coder 11, the AND circuit 90 is disabled. Accordingly, wheneverthe key-off inspection signal X is supplied, the storage in the key-ontemporary memory 48 is cleared. The key-off inspection signal X isapplied to an AND circuit in FIG. 6, and it is selected only for thefirst process period (the part (f) of FIG. 3) with the aid of the signalH1. A key-off inspection signal X1 selected in synchronization with thefirst process period is applied through an inverter 91 to the ANDcircuit 91, as a result of which the AND circuit 90 is disabled only forthe first process period. During this period, the contents stored in allthe channels in the key-on temporary memory 48 are cleared.

In the case where a key code N₁ -B₃ (or AN₁ -AB₂) based on thedepression of a new key which is not subjected to assignment issupplied, the aforementioned load signal LD is applied through the line88 and the OR circuit 89 to the key-on temporary memory 48, and a signal"1" is stored in the memory 48 in synchronization with the channel timeto which the relevant key code N₁ -B₃ (or AN₁ -AB₂) has been assigned.If, in the case where an already assigned key is depressed, the key codeN₁ -B₃ of that key is supplied, an assigned key-on signal AKON isprovided by an AND circuit (FIG. 6) in synchronization with thatassignment channel and it is applied through a line 92 to an AND circuit93. A second process period synchronization signal YH2 is applied to theother input terminal of the AND circuit 93. Therefore, the assignedkey-on signal AKON passes through the AND circuit 93 only for the secondprocess period, and it is applied through an OR circuit 89 to the key-ontemporary memory 48, where it is stored. Accordingly, the storage in thekey-on temporary memory 48 is cleared by the key-off inspection signal Xonce; however, as long as the key is depressed, a signal "1" is storedin that key's assignment channel before the next key-off inspectionsignal X is supplied. The second process period synchronization signalYH2 mentioned above is supplied by an AND circuit 108 in FIG. 4., and itis produced in accordance with the AND logic of the output of an ORcircuit (FIG. 4) receiving the outputs of the sixteen stages in theshift register (FIG. 4) and the second process period H2 of the decoder30 (FIG. 4). Accordingly, the signal YH2 is correctly in synchronizationwith the first through sixteenth channel times in the second processperiod.

The key-off inspection signal X generation period is of the order of 5ms. If the key code N₁ -B₃ of the key which was depressed is notsupplied by the key coder 11 during one generation period of the signalX at all, it is determined that the key has been released. Thisdetermination is carried out by an AND circuit 95. That is, it can bedetermined as follows: Key depression is being effected for the channelfor which a signal "1" is stored in the key-on temporary memory 48immmediately before the key-off inspection signal X is supplied, and keyrelease has been effected for the channel for which a signal "0" isstored therein. Thus, the output of the key-on temporary memory 48 isapplied through an inverter 94 to the AND circuit 95, thereby to disablethe latter 95 during the channel time for which the key release iseffected. A key-off inspection signal X1 having a 16-bit time width insynchronization with the first process period is applied to the ANDcircuit 95 from an AND circuit 107. Furthermore, the key-on signal KOoutputted by the key-on memory 46 is also applied to the AND circuit 95in order to detect whether or not a key has been depressed in thechannel for which the memory content is "0" in the key-on temporarymemory 48. Therefore, only when the key which has been depressed isreleased, that is, key release is effected, the AND condition of the ANDcircuit 95 is satisfied in the assignment channel time of that key. Theoutput "1" of this AND circuit 95 is a key-off signal KOF.

The key-off signal KOF is applied through an AND circuit 96 an ORcircuit 97 to an inverter 98, thereby to disable the self-holding ANDcircuit 81 of the key-on memory 46. As a result, the key-on signal KOstored in the key-on memory 46 is cleared in correspondence to thechannel for which the key-off signal KOF is provided. Accordingly, thekey-on signal KO is stored in the key-on memory 46 only for the periodduring which a key is being depressed. Since the key code memory circuit17 is not cleared by the key-off signal KOF, the relevant channelassignment is maintained even after the key release, and the key code N₁*-B₃ * concerning the key released is remains stored.

The key-off signal KOF is applied through an OR circuit 99 to thekey-off memory 49. This key off memory 99 operates to stored a signal"1" in synchronization with the assignment channel time of a key whichhas been released among keys which are being assigned to the channels. Akey-off memory signal KOFM outputted by the last state therein isself-held by means of an AND circuit 100 and the OR circuit 99. Appliedto the other input terminal of the AND circuit 100 is the output of theOR circuit 64 which are delivered through the line 88 and inverter 101.Therefore, if the load signal LD is provided during a channel time and anew assignment is effect, the storeage in that channel of the key-offmemory 49 is cleared. The key-off memory signal KOFM is applied throughan inverter 102 to one input terminal of an AND circuit 103, to theother input terminal of which the key-off signal KOF is applied. Whenthe key-off signal KOF is provided in a channel for the first time, thestorage in that channel of the key-off memory 49 is "0" . The output ofthe inverter 102 to which the signal KOFM is applied is "1" andtherefore the output of the AND circuit 103 has "1". This output "1" ofthe AND circuit 103 is utilized in the circuit shown in FIG. 7 as a newkey-off signal NKF representative of the fact that key release haseffected The new key-off signal NKF is produced only once in the channeltime to which the relevant key has been assigned, at the beginning ofthe key release.

The AND circuit, to which the key-off signal KOF is applied, is normallyenabled; however, when "a memory function" is effected, it is enabledduring the lower keyboard exclusive channel time. Upon operation of aswitch (not shown) for performing the memory function, a memory signalMM is provided by the key coder 11 and it is applied to one inputterminal of an AND circuit 104, to the other input terminal of which thelower keyboard exclusive channel signal YLK is applied. The output ofthe AND circuit 104 is applied through an inverter 105 to the ANDcircuit 96. Accordingly, where the "memory function" is performed, theAND circuit 96 is disabled during the lower keyboard exclusive channeltimes (cf. the part (c) of FIG. 3). Even if the key-off signal KOF isproduced in these channel times, the self-holding AND circuit 81 of thekey-on memory 46 is not disabled. Accordingly, in practice, even if akey is released in the lower keyboard, the key-on signal of the key-onmemory 46 is not cleared, and it is handled as if the key in the lowerkeyboard were continuously depressed. Thus, the tone concerning the keyis produced even after it is released. The above-described "memoryfunction" is advantageous in improving the automatic performance effect.Furthermore, since the embodiment is so designed that the lower keyboardexclusive channel can be used for automatic chords, automatic chords canbe produced even after key release.

The output of the AND circuit 104 is applied also to an AND circuit 106.The key-on signal KO of the key-on memory 46 which has been held evenafter the key release thanks of the "memory function" is cleared incorrelation to the output "1" of the AND circuit 106. A signal obtainedby inverting the output of the key-on temporary memory with an inverter94 and the output of the AND circuit 84 are applied to the remaininginput terminal of the AND circuit 106. The output of the inverter 94 israised to "1" in a channel for which key release is effected. If thischannel is the lower keyboard exclusive channel, then the output of theAND circuit 104 is also raised to "1". Therefore, the AND circuit 106 isdisabled in the relevant channel time. If, in this case, the AND circuit84 produces the lower key-board new key-on signal LNK, the output of theAND circuit 106 is raised to "1". The output "1" of the AND circuit 106is applied through the OR circuit 97 and the inverter 98 to the ANDcircuit 81 to disable the latter 81, as a result of which the storage ofthe relevant channel of the key-on memory 46 is cleared. Accordingly,the key-on signal KO held even after key release on account of the"memory function" is cleared when a key is newly depressed in the lowerkeyboard (or when the lower keyboard new key-on signal LNK is provided).

(KEY-ON AGAIN)

In the case where, immediately after a key is released, and the same keyis depressed again, a key-on again signal KAG is outputted from the ANDcircuit 44, and the assignment of the key is effected to a channeldifferent from the channel to which the key was assigned. The comparisonoutput EQ from the key code comparison circuit 18 is applied through theline 42 to the AND circuit 44, and furthermore the key code detectionsignal KON representative of the supply of a key code N₁ -B₃ (or AN₁-AB₂) and the output signal of the key-off memory 49 are applied to theAND circuit 44. Accordingly, under the conditions that the key code N₁-B₃ (or AN₁ -AB₂) being supplied now is equal (in keyboard also) to akey code N₁ *-B₃ * assigned to a channel, and the storage of the key-offmemory 49 in the channel to which that key code N₁ *-K₃ * has beenassigned is "1" which has provided coincidence is released), a signal"1" is outputted by the AND circuit 44. This output "1" of the ANDcircuit 44 is applied, as the key-on again signal KAG representative ofthe fact that a key released is depressed again immediately, to the ORcircuit 110, and it is further applied through as AND circuit 111 to adelay flip-flop 113 where it is stored. The output of the delayflip-flop 112 is applied to the OR circuit 57, and it is utilized forgenerating the new key-on signal KON.

(KEY-ON SIGNALS KO₁ and KO₂ Generation

The key-on signal KO of each channel outputted in time division mannerfrom the last, or 16th, stage of the key-on memory 46 is applied to ANDcircuits 113 and 114, which in turn output the first key-on signal KO₁and the second key-on signal KO₂, respectively, in response to thekey-on signal KO. The first key-on signal KO₁ is a signal whose level isswitched to "1" and "0" respectively according to the depression andrelease of a key assigned to the channel, and it is the same signal asthe key-on signal KO in a normal keyboard performance. A signal from theattack system key-on signal generating circuit 20 is applied through aline 115 to the other input terminal of the AND circuit 113. The signalon the line 115 is at "1" When an ordinary performance operation iscarried out by using the upper keyboard, the lower keyboard or the pedalkeyboard. Therefore, the AND circuit 113 is maintained enabled at alltimes, and the key-on signal KO is outputted as the first key-on signalKO₁. Accordingly, in this case, the first key-on signal KO₁ is generatedexactly in accordance with the depression of the key (tone) assigned tothe relevant channel. The output signal of a NAND circuit 116 of theattack system key-on signal generating circuit 20 is supplied to theline 115. The automatic bass chord selection signal ABC is applied toone input terminal of the NAND circuit 116. In the case where anautomatic bass chord performance is not selected, that is, in the caseof an ordinary keyboard performance, the signal ABC is at "0", and theNAND circuit 116 is disabled. Therefore, the signal on the line 115 isat "1" at all times.

Where an automatic bass chord performance is selected, the first key-onsignal KO₁ of a pedal keyboard tone is converted into a differentialsignal which is raised to "1" for a certain period in the beginning ofthe key depression. Since an automatic chord is produced in the pedalkeyboard's channel in case of an automatic bass chord performance, inpractice the first key-on signal KO₁ for an automatic bass becomes thedifferential signal. This can be achieved by applying the pedal keyboardexclusive channel signal YPK to the NAND circuit 116. Thus, only whenthe automatic bass chord selection signal ABC is supplied by the keycoder 11 and only in the pedal keyboard's exclusive channel time (thefirst channel time), the NAND circuit 116 is enabled. Three-bit countdata from a counter made up of an adder 117 comprising a 3-bit halfadder and 16-stage/3-bit shift registers 118 are applied to theremaining three input terminals of the NAND circuit 116. This counter isso designed as to carry out integration count by feeding data, which isdelayed by 16 channel times in the 16-stage shift registers 118, back tothe adder 117, and to carry out counting operations for the channels intime division manner. A count pulse T is applied through an AND circuit119 to the counter 117. The counter pulse T is provided by the timingsignal generating circuit 15 shown in FIG. 4.

Referring to FIG. 4, the one cycle finish signal Y48 outputted by theAND circuit 54 is applied to the count input terminal of afrequency-dividing counter 120. When all of the five bits of the outputof the counter 120 are raised to "1", an AND circuit 121 is operated, asa result of which a count pulse T having a time width of 48 μs isprovided by means of an AND circuit 122 and an OR circuit 123. Thiscount pulse T is obtained by subjecting the signal Y48 having a periodof 48 μs to 1/32 frequency division, and therefore it has a period ofabout 1500 μs (48×32). A test signal TEST applied to the OR circuit israised to "1" in a direct current mode only when the circuit operationis checked, and accordingly is not related to the original circuitoperation.

In the AND circuit in FIG. 6, the aforementioned count pulse T isselected only for the second process period, or 16 μs, with the aid ofthe second process period synchronization signal YH2. Accordingly, whenone count pulse T is produced, one count pulse is supplied at eachchannel time. A group of AND circuits 124 interposed between the adder117 and the shift registers 118 are enabled by the key-on signal fromthe key-on memory 46. Accordingly, where no key has been depressed in arelevant channel, the content of the relevant channel of the shiftregister 118 has been cleared, and counting the count pulses is effectedat the time of depressing a key. When seven count pulses T are suppliedafter depression of a key assigned to a channel is started, the 3-bitoutput of the shift register 118 has "1 1 1" ("7" in decimal notation)in that channel time. If the channel time is for the pedal keyboardexclusive channel, the signal YPK is raised also to "1". If in this casethe signal ABC is at "1", the NAND condition of the NAND circuit 116 issatisfied, and its output is switched to "0". When the output of theNAND circuit 116 is changed to "0", the output of the AND circuit 125 islowered to "0", as a result of which, the AND circuit 119 is disabled.Accordingly, the count pulse T is blocked at the relevant channel time,and the memory content "1 1 1" of the shift register for the relevantchannel is maintained unchanged.

The time interval which elapses from the time instant that depression ofa key is started until the output of the NAND circuit 116 has "0" isabout 10 ms (1.5 ms×7). For about 10 ms in the beginning of keydepression, the output of the NAND circuit 116 in a channel time towhich the key has been assigned is "1", and the AND circuit 113 isenabled. Accordingly, the key-on signal KO outputted by the key-onmemory 46 is selected only for about 10 ms in the beginning of keydepression, and it is outputted as the first key-on signal KO₁. Thus, inthe automatic bass chord performance, the first key-on signal KO₁ for atone (automatic bass) assigned to the pedal keyboard exclusive channelis provided only for about 10 ms. This short first key-on signal KO₁ isused for converting the amplitude envelope of an automatic bass tone(pedal keyboard tone) into an attack system envelope.

In the upper keyboard exclusive channel time, and the lower keyboardexclusive channel time, and in the pedal keyboard exclusive channel timewhere no automatic bass chord is effected, the output of the NANDcircuit 116 is at "1" at all times. The first key-on signal KO₁ isproduced exactly in accordance with a key depression operation(similarly as in the key-on signal KO) in these channel times. Thisfirst key-on signal KO₁ is used for giving a sustain system amplitudeenvelope to a musical tone.

The second key-on signal KO₂ outputted by the AND circuit 114 isemployed for converting the amplitude envelopes of the upper and lowerkeyboard tones into attack system envelopes. The term "attack systemenvelope" is intended to mean an envelope waveform which is employed forproducing a musical tone only for a short time period (about 10 ms forinstance) in the beginning of key depression. The output signal of aNAND circuit 126 in the attack system key-on signal generating circuit20 is applied to the other input terminal of the AND circuit 114. ThisNAND circuit 126 is enabled only when the upper keyboard exclusivechannel signal YUK or the lower keyboard exclusive channel signal YLK isapplied through an OR circuit 127 thereto. Similarly as in theabove-described NAND circuit 116, the output of the shift register 118is applied to the remaining input terminals of the NAND circuit 126.When it passes about 10 ms after depression of a key in the lowerkeyboard is started, or in the channel time to which the key has beenassigned, the output of the shift register 118 has "1 1 1", as a resultof which the NAND circuit 126 is operated, and its output is changed to"0". As a result, the AND circuit 114 is disabled in that channel time.Accordingly, the second key-on signal KO₂ is produced only for about 10ms after depression of a key in the lower keyboard is started. Withrespect to the upper keyboard tone and the lower keyboard tone,selective use of the first and second key-on signals KO₁ and KO₂ issuitably effected in the digital tone generator section 16. Theselective use of these signals KO₁ and KO₂ is controlled with the aid ofan envelope control signal EC supplied from the key coder 11.

(Truncate Control)

The new key-off signal NKF outputted by the AND circuit 103 and thekey-off memory signal KOFM outputted by the key-off memory 49 in FIG. 6are applied to the truncate circuit 21 in FIG. 7. In the truncatecircuit 21, the channel of a key which was released earliestly isdetected separately in the upper keyboard exclusive channel and thelower keyboard exclusive channel, and a truncate channel designationsignal TR is produced in synchronization with that channel time. Acounter is made up of a 4-bit adder 129 consisting of four half addersand a 16-stage/4-bit shift register 130. If, after keys assigned to thechannels are released, other keys are released, the numbers of times ofrelease of said other keys are counted in time division mannerseparately according to the channels by the counter. Accordingly, it canbe said that a key assigned to a channel having the maximum value in theshift register 130 is the key which was released earliestly.

When a key is released, the new key-off signal NKF is produced only oncein synchronization with a channel time to which the key is assigned.Therefore, if the counter comprising the adder 129 and the shiftregister 130 counts the number of new key-off signals NKF, the number oftimes of key release can be counted. In FIG. 7, the new key-off signalNKF is applied to AND circuits 131 and 132. A first process period upperkeyboard exclusive channel signal YUKI and a first process period lowerkeyboard exclusive channel signal YLK1 are applied to the remaininginput terminals of the AND circuits 131 and 132, respectively. Thesignal YUK1 is provided in synchronization with the lower keyboardexclusive channel time (the part (c) of FIG. 3) in the first processperiod (the part (f) of FIG. 3). Accordingly, when the new key-offsignal NKF is provided in the upper keyboard's channel time, the ANDcircuit 131 is operated. As a result, a signal "1" is inputted throughan OR circuit 133 into a delay flip-flop 135. On the other hand, wherethe new key-off signal NKF is provided in the lower keyboard's channeltime, the AND circuit 132 is operated. As a result, a signal "1" isinputted through an OR circuit 134 into a delay flip-flop 136. Thestorages in the delay flip-flops 135 and 136 are self-held through ANDcircuits 137 and 138, respectively. As the signal Y48 is applied to theAND circuits 137 and 138, the self-holding is released in the lastchannel time in the third process period (the part (h) of FIG. 3). Thus,when a depressed key is released in the uper keyboard or the lowerkeyboard, the new key-off signal NKF is inputted into the delayflip-flop 135 or 136 in the first process period, and the output of therelevant delay flip-flop 135 or 136 is raised to "1" in a DC mode forthe second and third process periods. The outputs of the delayflip-flops 135 and 136 are applied to AND circuits 139 and 140. A secondprocess period upper keyboard exclusive channel signal YUK2 and a secondprocess period lower keyboard exclusive channel signal YLK2 are appliedto the AND circuits 139 and 140, respectively. Accordingly, when a keyis released in the upper keyboard, the AND circuit 139 is enabled in itskeyboard's exclusive channel time in the second process period.Similarly, when a key is released in the lower keyboard, the AND circuit140 is enabled in its keyboard's exclusive channel time in the secondprocess period. The key-off memory signal KOFM is applied to theremaining input terminals of the AND circuits 139 and 140. As thekey-off memory signal KOFM is raised to "1" in synchronization with achannel time for which key release has been done already, the ANDcircuit 139 or 140 outputs a signal "1" only in these channel times. Theoutputs of the AND circuits 139 and 140 are applied through an ORcircuit 141 to the least significant bit in the adder 129. The adder 129operates to add "1" applied thereto from the OR circuit 141 to thepreceding addition result with respect to a relevant channel, which isstored in the shift register 130. The result of addition of the adder129 is applied through a group of AND circuits 142, an OR circuit 143and AND circuit 157 to the shift register 130, where it is stored. Thekey-off memory signal KOFM is applied to the other input terminal ofeach of the AND circuits 142, and when a depressed key is assigned to arelevant channel, the signal KOFM is switched to "0", as a result ofwhich the shift register 130 is cleared.

The output of the shift register 130 is applied to one input side (A) ofa comparator 144, to the other input side (B) of which the maximum valuememory data of a maximum value memory 145 or 146. Each of the maximumvalue memories 145 and 146 is made up of a 4-bit delay flip-flop. Themaximum value memory 145 is for the upper keyboard, and its memory datais outputted through a group of AND circuits 147 in the upper keyboardexclusive channel time. The maximum value memory 146 is for the lowerkeyboard, and its memory data is outputted through a group of ANDcircuits 148 in the upper keyboard exclusive channel time. The outputsof the groups of AND circuits 147 and 148 are applied through a group ofOR circuits 149 to the comparator 144. That is, the comparator 144 isused, in time division manner, commonly for the upper keyboard and thelower keyboard. When the output of the shift register 130 is greatedthan the memory data of the maximum value memory 145 or 146 (A>B), asignal "1" is applied to an output line 150 of the comparator 144 and itis applied to AND circuits 151 and 152, to which the first processperiod upper keyboard exclusive channel signal YUK1 and the firstprocess period lower keyboard exclusive channel signal YLK1 are applied,respectively. Accordingly, where the signal "1" on the line 150 is acomparison result concerning the upper keyboard, the AND circuit 151 isoperated; and where it is a comparison result concerning the lowerkeyboard, the AND circuit 152 is operated. The output "1" of the ANDcircuit 151 (152) controls the AND circuit group 153 (or 154) to clearthe old storage in the maximum value memory 145 (or 146) and to input anew maximum value data supplied by the shift register 130 into themaximum value memory 145 (or 146).

Thus, the maximum value data, that is, the highest number of times ofkey release is stored in the maximum value memory 145 or 146 during thefirst process period, and it is self-held for the second and thirdprocess periods. At the last channel time of the third process period,the one cycle finish signal Y48 is produced and it is applied to NORcircuits 155 and 156. As a result, the outputs of the NOR circuits 155and 156 are changed to "0", and the self-holding AND circuits of the ANDcircuit groups 153 and 154 are disabled.

The comparator 144 provides a coincidence output when the data appliedto the input side (A) coincides with the data applied to the input side(B). This coincidence output is applied, as the truncate channeldesignation signal TR, to the AND circuits 72 and 73 in FIG. 6. In otherwords, when the same data as the maximum value data stored in themaximum value memory 145 or 146 is outputted by the shift register 130,the truncate channel designation signal TR is provided issynchronization with the channel time.

The initial clear signal IC provided when the power switch is turned on,is applied to the NOR circuits 155 and 156 to clear the maximum valuememories 145 and 146. The initial clear signal IC is applied to the ORcircuit 99 in FIG. 6 to allow all the stages of the key-off memory 49 tostore "1". Therefore, immediately after the power switch is turned on,the key-off memory signals KOFM for all the channels have "1".Furthermore, the initial clear signal IC is applied through an ORcircuit 143 (FIG. 7) to the least significant bit of the shift register130, as a result of which the count value of the channels of the shiftregister 130 is changed to "0 0 0 1". This operation is effected in thecase where a key was depressed but it has not been released yet, inorder to prevent the production of the truncate channel designationsignal for the channel to which the key beind depressed has beenassigned. That is, in the beginning period after the power switch isturned on, the truncate channel designation signal TR is provided forthe channels to which no assignment has not been effected.

(5) Description of the Automatic Chord Key-on Signal Generating Circuit22:

When an automatic bass chord performance is selected, a chord toneproduction timing signal CG is supplied by the key coder 11. This signalCG is applied to a differentiation circuit comprising delay flip-flops158 and 159, an inverter 160 and an AND circuit 161 in the automaticchord key-on signal generating circuit 22 in FIG. 7, where it is shapedinto a differentiation pulse having a time width of 48 μs. Thisdifferentiation pulse from the AND circuit 161 is applied to the resetterminal of a 2-bit binary counter 162 for 1/4 frequency division, toreset the content of the counter 162 to "0 0". When the output of thecounter 162 has "0", the output of a NAND circuit 163 is raised to "1",thereby to enable an AND circuit 164. The count pulse T is appliedthrough the OR circuit 123 (FIG. 4) to the other input terminal of theAND circuit 164, and this count pulse T is selected by the AND circuit164 with the generation timing of the one cycle finish signal Y48. Theoutput of the AND circuit 164 is applied to the count input terminal ofthe counter 162. When three count pulses T are provided after thecounter 162 has been reset by the chord tone production timing signal,the content of the counter 162 has "1 1". As a result, the output of theNAND circuit 163 is switched to "0", and the AND circuit 164 isdisabled. Accordingly, counting the count pulse T by the counter 162 issuspended. Thus, the output of the NAND circuit 163 is at "1" for aboutthree periods of count pulse T after the generation of the chord toneproduction timing signal CG. This output "1" of the NAND circuit 163 isprovided, as an automatic chord key-on signal KO₃, through an ANDcircuit 165. Since the count pulse T has a period of about 1500 μs, thepulse width of the key-on signal KO₃ is about 4.5 ms (1.5 ms×3). Thelower keyboard key depression memory signal LKM is applied to the otherinput terminal of the AND circuit 165. Therefore, when a key isdepressed in the lower keyboard or a key code N₁ -B₃ concerning a chordis periodically supplied by the key coder 11, the signal LKM issustained at "1" to enable the AND circuit 165. This is because a chordtone is processed as a lower keyboard tone.

The lower keyboard key depression memory signal LKM can be obtained byselectively storing one, corresponding to the lower keyboard exclusivechannel, of the key-on signals KO outputted in time division manner bythe key-on memory 46 (FIG. 6). The lower keyboard exclusive channelsignal YLK is applied to an AND circuit 167 (FIG. 7), which is enabledonly at the lower keyboard exclusive channel time (the part (c) of FIG.3). The key-on signal KO is applied to the other input terminal of theAND circuit 167, and only the key-on signals KO concerning the lowerkeyboard are selected by this AND circuit 167, and are applied throughan OR circuit 168 to a delay flip-flop 169. The output of the delayflip-flop 169 is self-held by means of an AND circuit 170. The ANDcircuit 170 is disabled by the output "0" of a NOR circuit 171, to whichthe initial clear signal IC and a last channel signal C₁₆ are applied.The last channel signal C₁₆ is outputted by the AND circuit 25 in FIG.4, and it is repeatedly provided in synchronization with the lastchannel time of the time division time slot train, that is, thesixteenth channel's time slot (the part (a) of FIG. 3). Therefore, atthe sixteenth channel time at which the last channel signal C₁₆ isproduced, the AND circuit is disabled to release the self-holding of thedelay flip-flop 169.

The output of the delay flip-flop 169 is applied to an AND circuit 172which is enabled by the aforementioned last channel signal C₁₆.Therefore, the storage in the delay flip-flop 169 is inputted throughthe AND circuit 172 and an OR circuit 173 into a delay flip-flop 174,before its self-holding is released. The output of the delay flip-flop174 is self-hold by means of the OR circuit 173 and an AND circuit 175.The AND circuit 175 is disabled by the output "0" of the NOR circuit171. Therefore, the self-holding of the delay flip-flop 174 is releasedevery the sixteenth channel time at which the last channel signal C₁₆ isprovided. If a signal "1" is provided by the delay flip-flop 169 at thetime slot of the sixteenth channel, it is stored in the delay flip-flop174 again, and the delay flip-flop 174 is self-held until the followinglast channel signal C₁₆ is provided. Thus, if a key is depressed in thelower keyboard (if a tone is assigned to the lower keyboard exclusivechannel), the output of the delay flip-flop 174 is raised to "1" in a DCmode. This output "1" of the delay flip-flop 174 is utilized as thelower keyboard key depression memory signal LKM.

(6) Description of the Automatic Arpeggio Circuit 23

The automatic arpeggio circuit 23 operates in accordance with theautomatic arpeggio selection signal ARP delivered from the key coder 11,so that key codes N₁ *-B₃ (stored in the 2nd, 5th, 8th, 9th, 11th 12thand 15th stages of the shift register 26) corresponding to a pluralityof keys depressed in a particular keyboard (for instance the lowerkeyboard) among the key codes N₁ *-B₃ * stored in the channels of thekey code memory circuit 17 are selected in the order of tone pitches oneat a time in accordance with the arpeggio tone production timing. Thekey code N₁ *-B₃ * thus selected is delivered, as tha automatic arpeggiokey code AN₁ -AB₂, to the key code memory circuit 17 during the period(48 μs) during which the automatic arpeggio selection signal ARP isprovided, and it is stored in the arpeggio exclusive channel (the 14thchannel) of the circuit 17. When all the stored key codes N₁ *-B₃ *concerning the lower keyboard are selected by the automatic arpeggiocircuit 23 (when the tones of all the keys depressed in the lowerkeyboard are produced), the aforementioned stored key code N₁ *-B₃ * iscarried out by the circuit 23 again. In this case, in order that thepitches of the arpeggio tones which are produced in accordance with theselected key codes N₁ *-B₃ * are increased (or decreased) by one octavewhen compared with those of the preceding tone production, the octavecodes B₁ *-B₃ * of the key codes N₁ *-B₃ are changed to deliver thearpeggio key codes AN₁ -AB₂. By repeating the above-described operation,the control is effected in which arpeggio tones are repeatedly producedover a predetermined octave range one at a time at predetermined timeintervals in response to the depression of a plurality of keys in thelower keyboard. A further description of this automatic arpeggio circuit23 will be omitted.

Referring back to FIG. 7, the initial clear signal IC is applied to theset terminal (S) of the counter 162. Therefore, when the power switch isturned on, the content of the counter 162 is set to "1 1" and the outputof the NAND circuit 163 is switched to "0", thereby to stop the countoperation.

The detail fo the tone production assignment circuit 13 is as describedabove. As a result of the above-described assignment operation, the toneproduction of a key depressed in the upper keyboard is assigned to oneof the 3rd, 4th, 6th, 7th, 10th, 13th and 16th channels; the toneproduction of a key depressed in the lower keyboard or an automaticchord is assigned to one of the 2nd, 5th, 8th, 9th, 11th, 12th and 15thchannels; the tone production of a key depressed in the pedal keyboardor of an automatic bass is assigned to the 1st channel; and the toneproduction of an automatic arpeggio is assigned to the 14th channel. Thekey codes N₁ *-B₃ * of keys assigned to the respective channels areoutputted in time division manner by the key code memory circuit 17(FIG. 5) in synchronization with the respective channel times (the parts(a) through (e) of FIG. 3), and are applied to the data multiplexcircuit 14. The first and second key-on signals KO₁ and KO₂ are providedin time division manner separately according to the respective channels,and are applied to the data multiplex circuit 14 from the controlsection 19 (FIG. 6).

(7) Description of the data Multiplex Circuit 14

In the data multiplex circuit 14 in FIG. 5, the key information such asthe N₁ *-B₃ * and the key-on signals KO₁ and KO₂, supplied thereto intime division manner separately according to the channels from the toneproduction assignment circuit 13 is multiplexed, and for this purpose amultiplexing control signal BO is used. Furthermore, in the datamultiplex circuit 14, timing pulses Y₃₀, Y₃₁, Y₃₃, Y₃₄ and Y₃₆ areemployed for controlling the multiplexing of the control information,such as the evelope control signal EC, the damper signal DU, theautomatic bass chord selection signal ABC and the slow rock selectionsignal SR supplied thereto from the key coder 11, and of the automaticchord key-on signal KO₃.

The multiplexing control signal BO, as indicated in the part (n) of FIG.3, has a pulse width of 1 μs and a period of 3 μs.

As is apparent from the part (n) of FIG. 3, the signal BO occurs insynchronization with the 3rd, 6th, 9th, 12th, and 15 channel times inthe first process period (H₁), in synchronization with the 2nd, 5th,8th, 11th and 14th channel times in the second process period (H₂), andin synchronization with the 1st, 4th, 7th, 10th, 13th and 16th channeltimes in the third process period (H₃). This signal BO is provided by anOR circuit 199 in the timing signal generating circuit 15. An ANDcircuit 193 connected to the OR circuit 199 is enabled by the firstprocess period signal H₁. The outputs of the third, sixth, ninth,twelfth and fifteenth stages of the shift register 26 are appliedthrough an OR circuit 194 to the other input terminal of the AND circuit193. The second process period signal H₂ is applied to an AND circuit195 connected to the OR circuit 199. and the outputs of the second,fifth, eighth, eleventh and fourteenth stages of the shift register 26are applied through an OR circuit 196 to the AND circuit 195.Furthermore, the third process period signal H₃ is applied to an ANDcircuit 197, and the outputs of the first, fourth, seventh, tenth,thirteenth and sixteenth stages of the shift register 26 are appliedthrough an OR circuit 198 to the AND circuit 197. The outputs of theseAND circuits are applied to the OR circuit 199, as a result of which themultiplexing control signal BO is outputted by the OR circuit 199. Thus,as indicated in the part (n) of FIG. 3, the multiplexing control signalsBO are provided for all the channels in one process cycle.

In the data multiplex circuit 14, the pieces of key information and thepieces of control information concerning a channel are divided intothree parts which are delivered out one at a time. If it is assumed thatit takes one bit time (1 μs) for delivering each part of theinformation, then it will take three bit times (3 μs) for delivering thekey information and control information concerning one channel. For thispurpose, the multiplexing control signal BO generating period is 3 bittimes (3 μs). In the data multiplex circuit 14, the signal BO is shiftedsuccessively by one bit time in the three bit times, so that it can beutilized in three different ways. More specifically, the signal BO isdelayed successively by two delay flip-flops 201 and 206 (FIG. 5),thereby to provide a signal BO₁ delayed by one bit time and a signal BO₂delayed by two bit times. With the aid of these three signals BO, BO₁and BO₂, the key information of one channel is divided and deliveredsuccessively. The generation timing of the three signals BO, BO₁ and BO₂is shown enlarged in the parts (a), (b) and (c) of FIG. 8, respectively.

The original (not delayed) multiplexing control signal BO is applied toan AND circuit 200, and it is used for selecting the second key-onsignal KO₂ which is applied to the AND circuit 200 by the AND circuit114 in FIG. 6. The signal BO₁ delayed by one bit time is applied to ANDcircuits 202 through 205 from the delay flip-flop 201, and it isutilized to select the block code B₁ *-B₃ * and the first key-on signalKO. The signal BO₂ delayed by two bit times is applied to AND circuits207 through 210, and it is employed to select the note code N₁ *-N₄ *.Thus, with the aid of these signals BO, BO₁ and BO₂, the pieces of keyinformation KO₂, B₁ *-B₃ *, KO₁ and N₁ *-N₄ concerning one and the samechannel are selected. Therefore, after being delayed by one bit time bydelay flip-flops 215, 216 and 217, the block code B₁ *-B₂ * outputtedfrom the key code memory circuit 17 is applied to the AND circuit 202through 204. After being delay by one bit time by a delay flip-flop 218,the first key-on signal KO₁ from the AND circuit 113 in FIG. 6 isapplied to the AND circuit 205. On the other hand, the note code N₁*-N₄ * from the key code memory circuit 17 is delayed by two bit timesby delay flip-flop 219 through 222 and delay flip-flop 223 and 226 andis then applied to the AND circuit 207 through 210.

As a result, the key code N₁ *-N₄, B₁ *-B₃ outputted by the key codememory circuit 17 and the key-on signals KO₁ and KO₂ outputted by theAND circuits 113 and 114 during a channel time during which themultiplexing control signal BO is produced, are selected in the form ofthree parts which are shifted successively by one bit time within threebit times. The pieces of key information N₁ *-N₄ *, B₁ *-B₃ *, KO₁ andKO₂ (9-bit data in total) are applied to OR circuits 211 through 214, asa result of which a 4-bit data KC₁ -KC₄ is outputted by the channelprocessor 12 .Iadd.via parallel output transmission lines from the ORcircuits 211 through 214 to the tone generator 16.Iaddend.. Morespecifically, the second key-on signal KO₂ selected by the AND circuit200 with the aid of the multiplexing control signal BO is outputted asthe data KC₄ by the OR circuit 214, the block code B₁ *-B₃ * and firstkey-on signal KO₁ selected by the AND circuits 202 through 204 and 205are outputted as the data KC₁ -KC₄ by the OR circuits 211 through 214,and the note code N₁ *-N₄ * selected by the AND circuits 207 through 210with the aid of the signal BO₂ is outputted as the data KC₁ -KC₄ by theOR circuits 211 through 214. The states of the output data KC₁ -KC₄ ofthe channel processor 12 are as indicated in the part (d) of FIG. 8. Thepart (e) of FIG. 8 indicates the channels of the key information N₁*-N₄, B₁ *-B₃, KO₁ and KO₂ outputted in the form of data KC₁ -KC₄ by thechannel processor 12, and its typical example is the data KC₁ -KC₄concerning the third channel. As is apparent from the above description,the time division multiplex is effected in the order of the secondkey-on signal KO₂ (the first delivery timing), the block code B₁ *-B₃ *and first key-on signal KO₁ (the second delivery timing), the note codeN₁ *-N₄ * (the last delivery timing), in the typical example. The keyinformation N₁ *-B₃ *, KO₁ and KO₂ outputted by the tone productionassignment circuit section 13 when the delay multiplexing controlsignals BO₁ and BO₂ are provided is not used in the data multiplexcircuit 14. This key information N₁ *-B₃ *, KO₁ and KO₂ is utilized inthe data circuit 14 when the multiplexing control signal BO is providedin the relevant channel time (that is, it is multiplexed to be deliveredout). For example, the key information N₁ *-B₃, KO₁ and KO₂ outputted bythe tone production assignment circuit section 13 at the fourth andfifth channel times in the first process period (H₁) (cf. FIG. 3) is notutilized in the data multiplex circuit 14 as multiplex processconcerning the third channel is effected in the data multiplex circuit14 during those channel times, and in addition the AND circuits 200, 202through 205, and 207 through 210 are not so operated that the keyinformation N₁ *-B₃ *, KO.sub. 1 and KO₂ for the fourth and fifthchannels is selected. However, the multiplexing control signal BO occursat the fifth channel time of the second process period and at the fourthchannel time of the third process period as indicated in the part (n) ofFIG. 3, and in these cases time division multiplex process of the keyinformation of the fourth and fifth channels is effected. The part (0)of FIG. 3 indicates the time zones during which the time divisionprocess of the key information of the channels is carried out in thedata multiplex circuit 14, and the numerals indicated therein designatechannels where the process is effected. For convenience in description,in FIG. 8 the time division process time zones of from the sixth channelto the eleventh channel and from the seventh channel to the sixteenthchannel are omitted; however, the states of the data KC₁ -KC₄ in thetime division process time zones thus omitted are similar to thatconcerning the third channel.

In one process cycle from the first process period to the third processperiod, one multiplexing control signal BO is provided for each channeltime. Accordingly, in one process cycle (48 μs), the time divisionmultiplex process is carried for all the channels in the data multiplexcircuit 14. Since three bit times (3 μs) is required for processing onechannel, 489 bit times (48 μs) is required for processing sixteenchannels. The time division process time zones of the channels shown inthe part (O) of FIG. 3 are the time zones during which the keyinformation N₁ *-B₃ *, KO₁ and KO₂ of the keys or musical tones whichare assigned to the channels are delivered from the channel processor 12to the digital tone generator 16. These delivery time zones arecompletely different from the time division channel time of the toneproduction assignment circuit section 13, indicated in the part (a) ofFIG. 3.

At the timing of delivering the second key-on signal KO₂ as the dataKC₄, the data KC₁ -KC₃ are not used. Furthermore, for the pedalkeyboard, the block code provided is only two bits (B₁ *-B₂ *, and thethird bit (B₃ *) is not provided (cf. the NAND circuit 126 in FIG. 6).Accordingly, in delivering the pieces of information assigned to thefirst channel which is the pedal keyboard's exclusive channel, the dataKC₁ -KC₄ are not used at the first delivery timing, and furthermore thedata KC₃ (corresponding to the bit B₃ *) is not used at the nextdelivery timing. For the automatic arpeggio, the third bit (B₃ *) of itsblock code is not provided, and the first and second key-on signals KC₁and KC₂ are not used. Accordingly, in delivering the pieces ofinformation which are assigned to the fourteenth channel which is theautomatic arpeggio's exclusive channel, the data KC₁ -KC₄ are not usedat the first timing, and the data KC.sub. 3 and KC₄ are not used at thefollowing timing.

By utilizing the timing which is not used for the time divisionmultiplex delivery of the pieces of information of the channels, thetime division multiplex delivery of the envelope control signal EC, thedamper signal DU and other control information is carried out.

The timing pulse Y₃₀ is used to select the automatic chord key-on signalKO₃ and the automatic bass chord selection signal ABC respectively withAND circuits 227 and 228 (FIG. 5). This timing pulse Y₃₀ is outputted byan AND circuit 229 (in FIG. 4) at the thirtieth (30th) bit time from thefirst channel time in the first process period (that is, at the 14thchannel time in the second process period (cf. the part (p) of FIG. 3).While the timing pulse Y₃₀ occurs, the initial timing fortime-division-multiplexing the pieces of information of the 14th channelonly for the automatic arpeggio occurs in the data multiplex circuit 14.However, since the second key-on signal KO₂ is not used for theautomatic arpeggio as was described, the time pulse Y₃₀ is applied to aninverter 230, the output "0" of which is applied to an AND circuit 200to disable the latter 200. Thus, the second key-on signal KO₂ is notoutputted from the AND circuit 200. Instead of this, AND circuits 227and 228 are enabled by the timing pulse Y₃₀, as a result of which theautomatic chord key-on signal KO₃ applied to the AND circuit 227 from anAND ciruit in FIG. 7 is selected and applied to the OR circuit 214,while the automatic bass chord selection signal ABC applied to the ANDcircuit is selected and applied to the OR circuit 213. As a result, thesignal ABC and the key-on signal KO₃ are delivered, respectively as thedata KC₃ and the data KC₄, at the initial time (for the pulse Y₃₀generation timing) of the time division process time zone for the 14thchannel (cf. the part (d) of FIG. 8).

The timing pulse Y₃₁ is provided through an AND circuit 231 in FIG. 4 atthe next channel time of the timing pulse Y₃₀, or at the 15th channeltime in the second process period (cf. the part (p) of FIG. 3), and itis applied to an AND circuit 232 in FIG. 5. The slow rock selectionsignal SR is applied to the other input terminal of the AND circuit 232.This signal SR is selected with the timing of the timing pulse Y₃₁ andapplied to the OR circuit 214, thus being outputted as the data KC₄. Thetiming pulse Y₃₁ is provided at the second timing employed fordelivering the data of the arpeggio exclusive channel. As was describedbefore, in an ordinary delivery the first key-on signal KO₁ is deliveredto the line of the data KC₄ at said second timing. However, since thefirst key-on signal KO₁ is not used for the automatic arpeggio, thetiming pulse Y₃₁ is applied through an inverter 233 to an AND circuit205 (FIG. 5) thereby to disable the AND circuit 205 adapted to selectthe first key-on sigal KO₁. Accordingly, at the generation timing of thetiming pulse Y₃₁, the slow rock selection signal SR instead of the firstkey-on signal KO₁ is delivered as the data KC₄. At the second deliverytiming, the block code B₁ *-B₃ * is delivered as the data KC₁ -KC₃.However, in this connection, as the block code for automatic arpeggio isonly two bits (AB₁, and AB₂), no signal is provided to the line of thedata KC₃. Accordingly, at the second delivery timing of the data of thearpeggio exclusive channel (14th channel), the block code B₁ *, B₂ * isdelivered as the data KC₁ and KC₂ while the slow rock selection signalSR is delivered as the data KC₄.

The timing pulse Y₃₃ is provided through an AND circuit 234 in FIG. 4 atthe first channel time of the third process period (H₃) (cf. the part(p) of FIG. 3). In this operation, the multiplexing control signal BO isalso provided (the part (h) of FIG. 3), and the first timing fordelivering the data of the first channel, of the pedal keyboard'sexclusive channel, occurs. However, since the second key-on signal KO₂will not be used for the pedal keyboard tone, it is unnecessary todeliver the second key-on signal KO₂ at this first timing. In view ofthis, the first timing in the time division process time zone concerningthe pedal keyboard's exclusive channel is utilized for delivering areference data. For this purpose, the timing pulse Y₃₃ is applied to theOR circuits 211 through 214 to raise the levels of the data KC₁ -KC₄ to"1" (cf. the part (d) of FIG. 8). The data KC₁ -KC₄ whose contents aremade to "1 1 1 1" as described above is the aforementioned referencedata. This reference data "1 1 1 1" is utilized, as informationindicating a reference timing for discriminating the location timing ofvarious data which have been subjected to time division multiplex in thedata multiplex circuit 14, in the digital tone generator section 16.

As is apparent from Table 1 and Table 2 disclosed before, it isdetermined that the data "1 1 1 1" is not used for the note code N₁ -N₄(N₁ *-N₄ *) (at least, it is not used for the storage operation of thekey code memory circuit 17), and that the data "1 1 1" is not used forthe block code B₁ -B₃ (B₁ *-B₃ *). Therefore, the reference data "1 1 11" will never be mistaken for other key information and controlinformation.

The timing pulse Y₃₄ is produced one bit time later than the productionof the timing pulse Y₃₃ (cf. the part (p) of FIG. 3). That is, it isproduced through an AND circuit in FIG. 4. This timing pulse Y₃₄ isapplied to an AND circuit 236 in FIG. 5, as a result of which the dampersignal DU applied to the other input terminal of the AND circuit 236 isselected and applied to the OR circuit 213. The timing pulse Y₃₄ isfurther applied through an inverter 237 to the AND circuit 204 todisable the latter 204. Therefore, the third bit B₃ * of the block codeis blocked, and therefore the damper signal DU is outputted as the dataKC₃. In this case, as the block code B₁ *-B₃ * applied to the ANDcircuits 202, 203 and 204 is of the pedal keyboard, the third bit dataB₃ * is unnecessary (cf. Table 2). Accordingly, at the second timingconcerning the pedal keyboard's exclusive channel (1st channel), thedata B₁ *, B₂ *, DU and KO₁ are delivered as the data KC₁ -KC₄ asindicated in the part (d) of FIG. 8.

The timing pulse Y₃₆ is outputted by an AND circuit 238 (FIG. 4) at the4th channel time of the third process period (H₃) as indicated in thepart (p) of FIG. 3, and it is applied to an AND circuit 239 in FIG. 5,to the other input terminal of which the envelope control signal EC isapplied. The envelope control signal EC is selected with the timing ofthe timing signal Y₃₆, and is delivered, as the data KC₃, through the ORcircuit 213. While the timing pulse Y₃₆ occurs, the multiplexing controlsignal BO occurs also (cf. FIG. 3), as a result of which the initialdelivery timing of the data assigned to the 4th channel occurs.Accordingly, no key information to be delivered as the data KC₃ isavailable, and in this case the envelope control signal EC has beenassigned to the relevant time slot. Thus, at the initial timing in thetime division process time zone relating to the fourth channel, thesignals EC and KO₂ are delivered as the data KC₃ and KC₄, as indicatedin the part (d) of FIG. 8. .Iadd.The AND circuits 236 and 239 thuscomprise means for inserting commonly used envelope control information(e.g., the signals DU and EC) to certain of the output lines from thegates 211-214 at a suitable timing (FIG. 8) when the key information orkey-on information is not provided on these lines. .Iaddend.

The pieces of information ABC, SR, DU, EC and KO₃ and the reference data"1 1 1 1" are delivered out only in the time division process time zones(the part (o) of FIG. 3 and the part (e) of FIG. 8) of the 14th channel(arpeggios's exclusive channel), the 1st channel (pedal keyboard'sexclusive channel), and the 4th channel as indicated in FIG. 8. In thetime division process time zones of the 7th, 10th, 13th and 16thchannels which are executed successively thereafter, and in the timedivision process time zones of the 3rd, 6th, 9th, 12th, 15th 2nd, 5th,8th and 11th channels which are further repeatedly and successivelyexecuted, only the key information KO₂, B₁ *-B₃ *, KO₁ and N₁ *-N₄ isdelivered out in time division manner, as indicated in the time zone ofthe 3rd channel of FIG. 8. Thus, the time division delivery of thepieces of key information and control information assigned to thechannels are repeatedly carried out in the order indicated in the part(0) of FIG. 8. This repetition period is 48 μs corresponding to oneprocess cycle.

The total number of times slots for the multiplexed data KC₁ -KC₄outputted by the data multiplex circuit 14 is fourty-eight (48). Thestates of the data KC₁ -KC₄ at the time slots 1 through 48 are indicatedin FIG. 9, with the reference data "1 1 1 1" occurring in the time slot1.

From the above description and also from FIG. 3 and FIG. 8, the statesof the data KC₁ -KC₄ can be readily foreseen; however, to make sure, thedata are listed in FIG. 9, in which the marks (*) of the note codes N₁*-N₄ * and the block codes B₁ *-B₃ * are omitted for simplification.Furthermore, in FIG. 9, reference characters "U", "L", "P" and "ARP"designates channels where the tones of the upper keyboard, the lowerkeyboard, the pedal keyboard and the automatic arpeggio have beenassigned, respectively. Although not shown in FIG. 5, the circuitry isso formed that a test signal TEST is delivered to the line of the dataKC₂ at the same timing as that of delivering the envelope control signalEC (at the time slot 4 in FIG. 9) in the test of the circuit operation.This test signal TEST is not provided in the ordinary operation of theelectronic musical instrument, and it is provided only in testing thecircuit operation.

(8) Description of the Digital Tone Generator Section 16; (Analysis ofthe Time Division Multiplex Data in the Digital Tone Generator Section16)

The pieces of key information and control information which aretime-division-multiplexed in the form of 4-bit data KC₁ -KC₄ aresupplied, as the outputs of the channel processor 12, to the digitaltone generator section 16 from the data multiplex circuit 14.

FIG. 10 is a schematic diagram illustrating the digital tone generatorsection 16. A multiplex data analysis circuit 240 picks up the pieces ofkey information N₁ *-N₄ *, B₁ *-B₃, KO₁ and KO₂ and the pieces ofcontrol information ABC, SR, EC, DU and KO₃ separately out of the dataKC₁ 14 KC₄ delivered thereto from the data mutiplex circuit 14. In atone generator main section 241, sixteen tone generators 242 through 257are provided in correspondence to the channels. Furthermore, the tonegenerator main section 241 comprises shift registers 258 through 273 andlatch circuits 274 through 289 and 290 through 305 to distribute the keyinformation N₁ *-N₄ *, B₁ *-B₃ 0, KO₁ and KO₂ of the channels obtainedin the multiplex data analysis circuit 240 to the tone generators 242through 257 of the respective channels. That is, in the multiplex dataanalysis circuit 240, the data time-division-multiplex in the timedivision process time zone (3 bit times) concerning one channel areindividually taken out, and as the data of each channel obtained in themultiplex data analysis circuit 240 are subjected totime-division-multiplexing, they are distributed separately according tothe channels so as to be in static form by the tone generator mainsection 241. In order to control the timing of the analysis anddistribution of the time-division-multiplexed data, the reference data"1 1 1 1" is utilized. .Iadd.The multiplex data analysis circuit 240,the shift registers 258 through 273 and the latch circuits 274 through305 thus constitute a means for demultiplexing the delivered keyinformation KC₁ -KC₄ and for supplying each demultiplexed keyinformation to the assigned tone generator. .Iaddend.

The multiplex data analysis circuit 240 is shown in FIG. 11 in moredetail. The data KC₁ -KC₄ applied thereto from the data multiplexcircuit 14 are applied to an AND circuit 306, thereby to detect thetiming of delivering the reference data "1 1 1 1" (the reference timing,the time slot 1 in FIG. 9). The output of the AND circuit 306 is raisedto "1" at the reference data delivery timing. The output signal "1" ofthe AND circuit 306 which is provided in accordance with the referencedata will be called a reference pulse SP hereinafter (cf. the part (a)of FIG. 12). The reference pulse SP is inputted into a shift register307 and into a shift register 309 through an OR circuit 308. Thereference pulse SP is outputted from the first stage of the shiftregister 307 after one bit time, and it is applied to the strobeterminal (S) of a latch circuit 310 thereby to input the data KC₃applied to the data input terminal of the latch circuit 310 thereinto.At the next delivery time of the reference data (the time slot 2 in FIG.9), the damper signal DU is delivered as the data KC₃, and therefore thedamper signal DU is stored in the latch circuit 310. This storage ismaintained until the next damper signal DU is delivered as the data KC₃.A pulse SP₂ obtained by delaying the reference pulse SP by three bittimes is outputted from the third stage of the shift register 307 (thepart (b) of FIG. 12). This pulse SP₂ is applied to the strobe terminal(S) of a latch circuit 311 operating to input the input data thereinto.The data KC₂ and KC₃ are applied to the 2-bit latch circuit 311. Thetest signal TEST and the envelope control signal EC delivered as thedata KC₂ and KC₃ at the time slot 4 in FIG. 9 are latched with the aidof the pulse SP₂.

In the 2-stage shift register 309, the outputs of the two stages are fedback to the input side thereof through a NOR circuit 132 and an ORcircuit 308. A signal obtained by delaying the reference pulse SP by onebit time is outputted from the first stage of the shift register 309,and in this case the output of the NOR circuit 312 is at "0". Then, thesignal "1" of the first stage of the shift register 309 is shifted tothe second stage. In this case also, the output of the NOR circuit 312is at "0". Then, the outputs of the two stages of the shift register 309are changed to "0" at the third bit time (the time slot 4 in FIG. 9)from the generation timing of the reference pulse SP, while the outputof the NOR circuit 312 is raised to "1". Therefore, the signal "1" isread into the first stage of the shift register 309, and the output ofthe first stage is raised to "1" at the fourth bit time from thegeneration timing of the reference pulse SP. Thus, the signal "1" isinputted into each stage of the shift register 309 every 3 bit times(the part (c) of FIG. 12). The reference pulse SP is generated at thefirst delivery timing in the time division process time zone (3 bittimes). Therefore, the output BO₁ * of the first stage of the shiftregister 309 is generated at the second delivery timing, while theoutput BO₂ * of the second stage of the shift register 309 is generatedat the last delivery timing. Accordingly, the output signals BO₁ * andBO₂ * of the two stages of the shift register 309 are raised to "1"repeatedly in synchronization with the generation timing of the signalsBO₁ and BO₂ shown in the parts (b) and (c) of FIG. 8 (cf. the (d) and(e) of FIG. 12).

The signal BO₁ * is applied to the strobe terminal (S) of a latchcircuit 313, thus operating to store data (mainly being the block codeB₁ *-B₃ * and the first key-on signal KO₁) delivered out at the seconddelivery timing in the latch circuit 313. On the other hand, the signalBO₂ * is applied to the strobe terminal (S) of a latch circuit 314, thusoperating to store the note code N₁ *-N₄ * delivered at the lastdelivery timing in the latch circuit 314.

The latch circuit 313 has five latch positions to latch the block codeB₁ *, B₂ *, the automatic bass chord selection signal ABC, the firstkey-on signal KO₁ and the second key-on signal KO₂, respectively. Theslow rock selection signal SR is latched ta the same position as thefirst key-on signal KO₁, and the automatic chord key-on signal KO₃ islatch at the same position as the second key-on signal KO₂. The thirdbit data B₃ * of the block code B₁ *-B₃ * is not latched by the latchcircuit 313, because the note C₃ of the upper keyboard and the note C₂of the lower keyboard are not produced by the digital tone generatorsection 16. As is apparent from Table 2, the tone whose block code is "00 0" are only the tones (C₃ and C₂) in the upper and lower keyboards.Therefore, by cancelling these tones (C₃ and C₂) the tone range of theupper keyboard is made to be a range of C₃ #-C₇, and the tone range ofthe lower keyboard is made to be a range of C₂ #-C₆. Accordingly, inthis case, the bit B₃ * of the block code is unnecessary, and all theoctave ranges of the upper keyboard, the lower keyboard, the pedalkeyboard and the automatic arpegio can be determined from the contentsof the bits B₁ * and B₂ *. For this reason, the data bit B₃ * is notlatched by the latch circuit 313. The use of the bit B₃ * may beaccomplished by adding one latch position in the latch circuit 313.

The data KC₁ and KC₂ are applied to latch positions 313-1 and 313-2 inthe latch circuit 313. As the data KC₁ and KC₂ are latched at the seconddelivery timing with the aid or the signal BO₁ *, the bit B₁ * of theblock code is latched at the latch positions 313-1, while the bit B₂ *of the block code is latched at the latch position 313-2. The data KC₃is inputted to a latch position 313-3 of the latch circuit 313 through adelay flip-flop 315. The automatic bass chord selection signal ABC islatched at this latch position 313-3. However, since the automatic basschord selection signal ABC is delivered at the first delivery timing(the time slot 46 in FIG. 9), it does not coincide with the generationtiming of the signal BO₁ * if it is left as it is. Therefore, the dataKC₃ is delayed by one bit time by means of a delay flip-flop 315, sothat the timing of the automatic bass chord selection signal ABCcoincides with that of the signal BO₁ *.

The data KC₄ is inputted to a latch position 313-4 of the latch circuit313. Since the data KC₄ is latched at the second delivery timing withthe aid of the signal BO₁ *, the first key-on signal KO₁ is latched atthe latch position 313-4. However, it should be noted that this iseffected for the first through thirteenth channels and the fifteenth andsixteenth channels. As the data KC₄ at the second delivery timing withrespect to the fourteenth channel is the slow rock selection signal SR(cf. the time slot 47 in FIG. 9), the slow rock selection signal SR islatched at the latch position 313-4 only in the time division processtime zone of the fourteenth channel.

The data KC₄ is applied through a delay flip-flop 316 to a latchposition 313-5 of the latch circuit 313. The second key-on signal KO₂ orthe automatic chord key-on signal KO₃ is latched at the latch position313-5. These key-on signals KO₂ and KO₃ are delivered at the firstdelivery timing in the time division process time zone of each channel.Therefore, the data KC₄ is delayed by one bit time by the delayflip-flop 316, so that the timing of the key-on signal KO₂ or KO₃coincides with that of the signal BO₁ *. As is clear from FIG. 9, thesecond key-on signal KO₂ is latched in the latch position 313-3 in thetime division process time zones of the second through thirteenth,fifteenth and sixteenth channels, and the automatic chord key-on signalKO₃ is latched in the latch position 313-5 in the time division processtime zone of the fourteenth channel.

The signal BO₂ * outputted from the second stage of the shift register309 is applied to the strobe terminal (S) of a latch circuit 314. Thedata KC₁ -KC₄ are applied to the 4-bit latch circuit 314. The data KC₁and KC₂ are applied respectively through OR circuits 317 and 318 to thelatch circuit 314. Furthermore, the data KC₁ and KC₂ are applied to aNOR circuit 319 to which the data KC₃ is applied through an inverter320. This NOR circuit 319 is to detect the fact that the note code N₁*-N₄ * (0 0 1 1) of the note C has been delivered. When the cata KC₁,KC₂, KC₃ corresponding to the bits N₁ *, N₂ *, N₃ * has "0 0 1", the NORcircuit is operated to output a signal "1". This output signal "1" ofthe NOR circuit 319 is applied through the OR circuits 317 and 318 tothe latch circuit 314. Accordingly, the note code N₁ *-N₄ * of the noteC is changed from the value "0 0 1" to its original value "1 1 1 1"which is latched in the latch circuit 314. The note code N₄, N₃, N₂, N₁of the note C in the force stage of the digital tone generator section16 has been made to be "1 1 0 0" because it may not be mistaken for thereference data "1 1 1 1".

The contents of the latch circuit 313 and 314 are rewritten every timedivision process time zone of each channel (every 3 bit times).Accordingly, it can be understood from the outputs of the latch circuits313 and 314 that the note codes N₁ *-N₄ *, block codes B₁ *, B₂ *, andkey-on signal KO₁ and KO₂ of the notes assigned to the channels aresuccessively in time division manner (with 3-bit time width). On theother hand, the automatic bass chord selection signal ABC, the slow rockselection signal SR, and the automatic chord key-on signal KO₃ aresimultaneously outputted by the latch circuit 313 in the time zone forthe fourteenth channel.

As is indicated in the parts (f) and (g) of FIG. 12, the timing of thedata B₁ *-KO₂ (KO₃) outputted by the latch circuit 313 is later by onebit time than that timing of the data N₁ *-N₄ * outputted by the latchcircuit 314. In the part (f) and (g) of FIG. 12, the timing of the dataB₁ -KO₂ (KO₃) outputted by the latch circuit 313 and the timing of thedata N₁ *-N₄ * outputted by the latch circuit 314, and numerals thereindesignates the channels, the order of which is the same as that shown inFIG. 9.

The outputs of the latch circuits 313 and 314 are delayed by one bittime by flip-flop groups 321 and 322, respectively. The timing thusdelay is indicated by the broken lines in the parts (f) and (g) of FIG.12. After being delayed by the delay flip-flop group 322, the block codeB₁ *, B₂ * is applied to a decoder 323, where it is decoded into dataOS₁, OS₂, OS₃ and OS₀ for every octave. The relationships between theinput and output of the decoder are as indicated in Table 3 below:

                  TABLE 3                                                         ______________________________________                                        Block Code                                                                    B.sub.2 *   B.sub.1 *                                                                            Octave Selection Data                                      ______________________________________                                        0           1      OS.sub.1                                                   1           0      OS.sub.2                                                   1           1      OS.sub.3                                                   0           0      OS.sub.0                                                   ______________________________________                                    

The relationships between the tone ranges and the octave selection dataOS₁, OS₂, OS₃ and OS₀ in each keyboard can be readily understood fromTable 2 and Table 3.

After being delayed by the delay flip-flop group 322, the three highersignificant bits, or the note code data N₁ *, N₂, N₃, are applied to adecoder 324, where they are decoded into six note selection data n₁through n₆. The relationships between the input and the output of thedecoder 324 are as indicated in Table 4.

                  TABLE 4                                                         ______________________________________                                        N.sub.1 *                                                                           N.sub.2 *                                                                              N.sub.3 *                                                                            Note Selection Data                                                                         Note                                      ______________________________________                                        0     0        1      n.sub.1       C♯                                                                     G                                    0     1        0      n.sub.2       D    G♯                       0     1        1      n.sub.3       D♯                                                                     A                                    1     0        1      n.sub.4       E    A♯                       1     1        0      n.sub.5       F    B                                    1     1        1      n.sub.6       F♯                                                                     C                                    ______________________________________                                    

As is apparent from Table 4, each of the note selection data n₁ -n₆corresponds to two notes. The true correspondence of a note selectiondata to one of the two notes can be determined by the fourth bit's notecode data N₄ which are simultaneously applied. The reason for this isclear from Table 1 and Table 4. That is, if the data N₄ *(N₄) is "0",then the note is one of the tones C# through F#; and if it is "1", thenit is one of the tones C through F. Of course, this is under thecondition that the note code N₁ *-N₄ * of the note C is converted into"1 1 1 1".

The reason why the note codes N₁ *-N₄ and the block codes B₁ *, B₂ * aredecoded into the note selection data n₁ -n₆, N₄ * and octave selectiondata OS₁ -OS₀, is as follows: In accordance with these selection data n₁-n₆, N₄ * and OS₁ -OS₀, the tone generators 247 through 257 (FIG. 10)are allowed to directly select the tone source signals of the tonesassigned to the relevant channels.

The note selection data n₁ -n₆ and N₄ * are applied, in a parallel mode,to the latch circuits 290-305 provided for the tone generators 242-257of the channels, while the octave selection data OS₁, OS₂, OS₃ and OS₄are applied, in a parallel mode, to the latch circuits 274-289 providedrespectively for the tone generators 242-257. The data buses 328 and 329in FIG. 11 are the same as the data buses 328 and 329 in FIG. 10. Thekey-on signal KO₁ and the pieces of control information ABC . . . whichare outputted to the data bus 329 with the same timing as that of theoctave selection data OS₁ -OS₀ are not always applied to all of the tonegenerators 242-257, because these pieces of information are used for thelimited keyboards.

This will be described in more detail. The first key-on signal KO₁introduced to a line 326 thrugh the delay flip-flop group 321 from thelatch position 313-4 in the latch circuit 313 is used with the pedalkeyboard's channel. The automatic bass chord selection signal ABC, theslow rock selection signal SR, and the automatic chord key-on signal KO₃introduced to lines 325, 326 and 327 from the latch positions 313-3,313-4 and 313-5 of the latch circuit 313 are used for the automaticchord's amplitude envelope control. For this purpose, in the tonegenerator main section 241 in FIG. 10, an automatic chord envelopecontrol section 330 is provided, whereby the signals ABC, SR and KO₃ arelatched, in a parallel mode, by a latch circuit 331 and are supplied tothe control section 330.

In the upper keyboard and the lower keyboard, the first key-on signalKO₁ and the second key-on signal KO₂ are properly used in accordancewith the envelope control signal EC. Such proper use is not effected forthe pedal keyboard in this embodiment. In addition, the damper signal DUis used for the upper keyboard tone only. Thus, after being processed atthe side of the multiplex data analysis circuit 240, the key-on signalsKO₁ and KO₂ concerning the upper keyboard and the lower keyboard aresupplied to the tone generator main section 241.

The first key-on signal KO₁ outputted through the delay flip-flop group321 from the latch position 313-4 in the latch circuit 313 is applied toan AND circuit 332 and to an AND circuit 334 through an inverter 333.The damper signal DU stored in the latch circuit 310 is applied to theother input terminal of the AND circuit 334. Accordingly, the output ofthe AND circuit 334 is raised to "1" with "KO₁ ·DU". In the upperkeyboard's exclusive channel, the first key-on signal KO₁ is provided incompliance with the key depression. Therefore, the fact that "KO₁ is "1"means that "KO₁ " is "0", that is, the key release has been effected.Accordingly, if a key of the upper keyboard is released where the dampmode has been selected (DU="1"), the output signal KO₁ ·DU of the ANDcircuit 334 is raised to "1". This signal KO₁ ·DU instructs that theproduction of a tone which is in a damp state by key release should bequickly finished.

The second key-on signal KO₂ outputted through the delay flip-flop group321 from the latch position 313-5 of the latch circuit 313 is applied toone input terminal of an AND circuit 335, to the other input terminal ofwhich the envelope control signal EC stored in the latch circuit 311 isapplied. This signal EC is further applied through an inverter 336 tothe AND circuit 332. The outputs of the AND circuits 332 and 335 areapplied to an OR circuit 337. Thus, the condition expression of theoutput of the OR circuit 337 is (KO₁ ·EC+KO₂ EC). This output signal(KO₁ EC+KO₂ EC) of the OR circuit 337 is utilized as an upper keyboardkey-on signal (or a lower keyboard key-on signal) representative of thekey depression time of an upper keyboard tone (or a lower keyboardtone). That is, when the envelope control signal EC is at "0", the samesignal as the first key-on signal KO₁ is outputted, as the upper orlower keyboard key-on signal, by the OR circuit 337. This means that theupper keyboard tone or the lower keyboard tone is produced only for theperiod of time during which the key is actually depressed. When theenvelope control signal EC is at "1", a signal having the same timewidth as that of the second key-on signal KO₂ is outputted by the ORcircuit 337. Since the second key-on signal KO₂ is a (short) signallasting for about 10 ms like an attack signal, the upper keyboard toneor the lower keyboard tone is produced only for the short period of time(about 10 ms) immediately after the key depression. The relationshipsbetween the tone generators 242 through 257 and the tone productionchannels and the keyboards are as indicated in Table 5.

                  TABLE 5                                                         ______________________________________                                        Tone Generator                                                                               Channel   Keyboard                                             ______________________________________                                        242           1          Pedal keyboard                                       243           4                                                               244           7                                                               245           10         Upper keyboard                                       246           13                                                              347           16                                                              248           3                                                               249           6                                                               250           9                                                               251           12         Lower keyboard                                       252           15                                                              253           2                                                               254           5                                                               255           8                                                               256           11                                                              257           14         Automatic arpeggio                                   ______________________________________                                    

The tone generators 244 through 248 and 251 through 255 are not shown inFIG. 10. As is apparent from the above description and Table 5, thelatch circuits 274 through 289 and 331 to which the pieces of controlinformation ABC, etc. and the key-on signal KO₁ are applied through thedata bus 329 by the multiplex data analysis circuit 240 are as indicatedin Table 6 below:

    ______________________________________                                        Data            Latch Circuit                                                 ______________________________________                                        ABC on the line 325                                                                           331                                                           SR on the line 326                                                                            331                                                           KO.sub.3 on the line 327                                                                      331                                                            ##STR1##        275 through 281, and 282 through                              ##STR2##                                                                     on the line 339 288                                                           KO.sub.1 on the line 326                                                                      274                                                           ______________________________________                                    

The reference pulse SP₂ (the part (b) of FIG. 12) outputted from thethird stage in the shift register 307 in FIG. 11 is applied through theline 340 to the shift register 258 in FIG. 10, and it is applied also tothe strobe terminal of the latch circuit 274 (FIG. 10). The (timing)relationships between the data supplied to the data bus 329 and thechannels are as indicated by the broken lines in the part (f) of FIG.12. As a apparent from the parts (b) and (f) of FIG. 12, when the pulseSP₂ is provided, the center time slot of the first channel's time zone(3-bit time width) occurs, and accordingly the key-on data KO₁ and theoctave selection data OS₁ -OS₀ concerning the first channel have beenpositively inputted into the latch circuit 274 with the timing of thepulse SP₂, and these data OS₁ -OS₀ and KO₁ are latched by the latchcircuit 274 with the aid of the pulse SP₂.

Pulses SP₅, SP₈, SP₁₁ . . . SP₂₃, SP₂₆, . . . SP₄₄, and SP₄₇ obtained bysuccessively delaying the pulse SP₂ by three bit times by 3-stage shiftregisters 248, 259 . . . 265, and 266 . . . 272 are applied to thestrobe terminals (S) of the latch circuits 275 through 289 and 331provided for the tone generators 243 through 257, respectively. Thesepulses SP₅, SP₈, . . . SP₂₃, SP₂₆, . . . SP₄₄ and SP₄₇ spaced at threebit time intervals correspond to the delivery timing of the data OS₁-OS₀, KO₁, etc. of the channels which are delivered to the data bus 329,respectively. Accordingly, the octave data OS₁ -OS₀, the key-on signalKO₁, etc. of the channels which are subjected to time division multiplexon the data bus 329 are distributed separately according to the channels(to the tone generators 242 through 257), and are stored in the latchcircuits 275 through 289 of the channels, respectively. Furthermore, thesignals ABC, SR and KO₃ relating to the automatic chord are stored inthe latch circuit 331 in response to the pulse SP₄₇ with the timing ofthe fourteenth channel.

Pulses SP₃, SP₆, SP₉ . . . SP₂₄, SP₂₇. . . SP₄₅ and SP₄₈ outputted fromthe fist stages of the shift registers 258 through 273 are applied tothe strobe terminals (S) of the latch circuits 290 through 305 providedfor the channels, respectively. These pulses SP₃, SP₆, SP₉ . . . SP₂₄,SP₂₇ . . . SP₄₅ and SP₄₈ are also provided at three bit time intervals,but they are delayed by one bit time from the aforementioned pulses SP₂,SP₅, SP₈ . . . SP₂₃, SP₂₆ . . . SP₄₄ and SP₄₇ (cf. the part (b) of FIG.12). The note selection data n₁ through n₆ are applied through a noteselection data bus 328 to the latch circuits 290 through 305,respectively. The (timing) relationships between the data n₁ through n₆supplied to the note selection data bus 328 and the channels are asindicated by the broken lines in the part (g) of FIG. 12. Accordingly,in the channels, the timing of generating the pulses SP₃, SP₆, . . .SP₂₄, SP₂₇, . . . SP₄₅ and SP₄₆ from the first stages of the shiftregisters 258 through 273 coincides with the timing of applying the noteselection data n₁ through n₆ concerning the relevant channels to thelatch circuits 290 through 305 through the data bus 328. Accordingly,the note selection data n₁ -n₆ and N₄ * of the channels which aresubjected to time division multiplex on the data bus are distributedseparately according to the channels (to the tone generators 242 through257), and are stored in the latch circuits 290 through 305 provided forthe channels, respectively.

That is, the note selection data n₁ -n₆ and N₄ * and the octaveselection data OS₁, OS₂, OS₃ and OS₀ concerning the tones assigned tothe channels are maintained stored in the latch circuits 274 through 289and 290 through 305 provided for the tone generators 242 through 257,respectively. Maintained stored in the latch circuit 274 for the tonegenerator 242 is the first key-on signal KO₁ of a tone assigned to therelevant channel. When an automatic bass tone is assigned to the pedalkeyboard's exclusive channel, the attack system (about 10 ms) key-onsignal KO₁ is stored in the latch circuit 274 for the pedal keyboard'sexclusive channel, as was described before.

The key-on signals (KO₁ ·EC+KO₂ ·EC) and the damp instruction signals(KO·DU) of tones assigned to the relevant channels are maintained storedin the latch circuits 275 through 281 provided for the tone generators242 through 249 concerning the upper keyboard, respectively.

The key on signals (KO₁ ·EC+KO₂ ·EC) of tones assigned to the relevantchannels are maintained stored in the latch circuits 282 through 288provided for the tone generators 250 through 256 concerning the lowerkeyboard, respectively.

The note selection data n₁ -n₆ and N₄ *, the octave selection data OS₁-OS₀, the key-on signals KO₁ and (KO₁ ·EC+KO₂ ·EC) or the dampinstruction signals (KO₁ ·DU) maintained stored in the latch circuits274 through 289 and 290 through 305 are utilized in the tone generators242 through 257 to cause the respective tone generators 242 through 257to produce the tones assigned to the respective channels. Furthermore,the automatic bass chord selection signal ABC, the slow rock selectionsignal SR, and the automatic chord key-on signal KO₃ stored in the latchcircuit 331 are utilized in the automatic chord envelope control section330. The output of the automatic chord envelope control section 330 isused to control the envelopes of tones produced by the lower keyboard'stone generators 250 through 256. In this connection, it should be notedthat the automatic chord is produced as the lower keyboard tone. In thelower keyboard's tone generators 250 through 256, damp characteristicsare given to the envelopes of automatic chords under the control of theautomatic chord envelope control section 330.

The tone generators 242 through 257 operate to produce the musical tonesignals (tone source signals) of notes specified by the note selectiondata n₁ -n₆ and N₄ * stored in the respective latch circuits 290 through305. These musical tone signals (tone source signals) are produced inthe octave ranges specified by the octave selection data OS₁ -OS₀ storedin the respective latch circuits 274 through 289. The tone generators242 through 257 are so designed that they can produce musical tonesignals concerning a plurality of foot systems at the same time.

For instance an 8-foot system pedal keyboard musical tone signal P8' anda 16-foot system pedal keyboard musical tone signal P16' are provided bythe tone generator 242 of the pedal keyboard's exclusive channel. Theseven tone generators 243 through 249 of the upper keyboard's exclusivechannel provide 2-foot system 4-foot system, 8-foot system and 16-footsystem upper keyboard musical tone signals U₂ ', U₄ ', U₈ ' and U₁₆ '.The output musical tone signals of the tone generators 242 through 249are mixed for every foot system and are provided through the digitaltone generator 16. In the lower keyboard's tone generators 250 through256, 2-foot system, 4-foot system and 8-foot system lower keyboardmusical tone signals L₂ ', L₄ ' and L₈ ' are provided, and furthermore4-foot system and 8-foot system automatic chord signals A₄ ' and A₈ 'are provided. In an ordinary lower keyboard performance, the lowerkeyboard musical tone signals L₂ ', L₄ ' and L₈ ' are produced; and inan automatic bass chord performance, the automatic chord signals A₄ 'and A₈ ' are roduced. These musical tone signals L₂ ', L₄ ' and L₈ ' andautomatic chord signals A₄ ' and A₈ ' are subjected to mixing for everyfoot system, and are outputted by the digital tone generator section 16.The tone generator 257 corresponding to the automatic arpeggio'sexclusive channel produces 2-foot system and 4-foot system automaticarpeggio musical tone signals AR₂ ' and AR₄ '.

The tone generators 242 through 257 may be so designed that each canproduce musical tone signals covering all the tone pitches. However, inthis case, the construction of each of the tone generators 242 through257 becomes necessarily intricate which will result in an increase ofmanufacturing cost. In view of this, a frequency division signalgenerating section 341 is provided as shown in FIG. 10, so that musicaltone signals covering all the tone pitches which can be provided by thisembodiment are produced in accordance with a frequency division system.The submultiple frequency signals generated by the submultiple frequencysignal generator section 341 are supplied to the tone generators 242through 257, so as to select the frequency division signal whichcorresponds to the contents of the note selection data n₁ -n₆ and N₄ *and the octave selection data OS₁ -OS₀ stored in the latch circuits 274through 289 and 290 through 257. For simplification, a connectiondiagram illustrating the supply of the submultiple frequency signals(tone source signals) having various frequencies to the tone generators242 through 257 from the submultiple frequency signal generating circuit431 is omitted from FIG. 10.

Detailed description of the tone generator

The generator 341 comprises wave generation circuits 341-1 through341-12 corresponding respectively to the twelve notes C#, D, D#, . . . Band C. As the wave generation circuits 341-1 through 341-12, themultiplexed data generator described in the specification of U.S. patentapplication Ser. No. 915,239 filed 6/13/78, and assigned to the assigneeof the present case may, for example, be employed. In such wavegeneration circuits, a master clock pulse φM is counted by a maximumlength counter 343 capable of variably setting its modulo number as isschematically shown in the circuit 341-1 so as to produce a pulse ofhigh frequency corresponding to the note C and a plurality ofsubmultiple frequency wave data is produced from this pulse by means ofa submultiple frequency data forming circuit consisting of seriallyconnected shift registers 344 and a one-bit adder 345. In this manner, aplurality of submultiple frequency data corresponding to the frequencyof the note C is outputted through a submultiple frequency data line342-1. Each submultiple frequency data is outputted on the submultiplefrequency data line 342-1 each time at least the value of the bitcorresponding to the highest frequency is turned to "1" or "0". In otherwords, the timing at which the value of the bit corresponding to thehighest frequency is turned over is a minimum unit of variation of thesubmultiple frequency data. The other circuits 341-2 through 341-12 forthe notes C# through B are of a similar construction except that themodulo number of the maximum length counter 343 is different dependingupon the frequency of the note. FIG. 14 illustrates an example of astate of the submultiple frequency data serially outputted from the wavegeneration circuit 341-1 (or 341-2 through 341-12) on the submultiplefrequency data line 342-1 (or 342-2 through 341-12). A timing pulse TPappears preceding to each of submultiple frequency data train, D₁, D₂ .. . The timing at which the data train D₁, D₂ . . . exists is known byexistence of the timing pulse TP. In the data train D₁, D₂ . . . ,submultiple frequency data Q₂ -Q₇ is serially outputted following thetiming pulse TP. The submultiple frequency data Q₂ -Q₈ provided on thedata lines 342-1 through 342-12 is supplied to the upper keyboard tonegenerators 243 through 249, the lower keyboard tone generators 250through 256 and the automatic arpeggio tone generator 257. The data onthe data lines 342-1 through 342-12 is not applied to the pedal keyboardtone generator 242 which operates in response to a different clockpulse. This is because the master clock pulse φM itself isfrequency-modulated for producing a vibrato effect in this embodiment.In other words, the different pulse is used in the pedal keyboard tonegenerator 242 so that the vibrato effect is produced only in the upperand lower keyboards and not in the pedal keyboard.

Upper keyboard tone generator

As an example of the upper keyboard tone generators 243 through 249, thetone generator 243 concerning the fourth channel is shown in detail inFIG. 15. The other tone generators 244 through 249 are of the sameconstruction.

With reference to FIG. 15, the submultiple frequency data on the lines342-1 through 342-12 is applied to a note selection circuit 356. Thenote selection circuit 346 selects submultiple frequency data Q₂ -Q₇ ona single one of the lines 342-1 through 342-12 in accordance with thenote selection data n₁ -n₆ and N₄ * concerning the specified channelstored in the latch circuit 291. For example, if the note C is assignedto the fourth channel, the note selection data n₁ -n₆ and N₄ * is madeup of n₆ and N₄ * which are "1" and n₁ -N₅ which are all "0" (Table 5).Accordingly, an AND gate 347 in the note selection circuit 346 isenabled to select the submultiple frequency data Q₂ -Q₇ for the note Con the line 342-1.

The submultiple frequency data Q₂ -Q₇ selected by the note selectioncircuit 346 is applied to a seven-stage shift register 348 through aline 463. As shown in FIG. 14, the timing pulse TP appears immediatelybefore the submultiple frequency data Q₂ -Q₇. When this timing pulse TPhas entered the first stage of the shift register 348, contents of thepreceding second through seventh stages are all "0". The timing pulse TPappears at the top of the submultiple frequency data train and no dataexists at least during 6 bit time before the timing pulse TP appears.The outputs of the second through seventh stages of the shift register348 are applied to a NOR gate 349 without any modification and theoutput of the first stage is applied to the NOR gate 349 after beinginverted by an inverter 350. Accordingly, when the timing pulse TP hasentered the first stage of the shift register 348, the output of the NORgate 349 is turned to "1". A set-reset type flip-flop 351 is set by theoutput "1" of the NOR gate 349 and the set output of the flip-flop 351is applied to an AND gate 353 after being delayed by 1 bit time by adelay flip-flop. When the timing pulse TP of the first stage of theshift register 348 has entered the seventh stage after lapse of 6 bittime, the flip-flop 351 is reset and the AND gate 351 is enabled by theoutput "1" of the seventh stage. The output "1" of the AND gate 353 isapplied to a strobe terminal (S) of a latch circuit 354. Since theoutput of the delay flip-flop 352 falls to "0" 1 bit later, the outputof the AND gate 353 is "1" only during 1 bit time. At this time, thedata Q is in the sixth stage of the shift register 348, the data Q₃ inthe fifth stage, the data Q₄ through Q₇ in the fourth down through thefirst stages, and, accordingly, the data Q₂ -Q₇ is loaded into the 6-bitlatch circuit 354 in parallel. In the above described manner, the serialsubmultiple frequency data Q₂ -Q₇ is converted to parallel data and heldby the latch circuit 354. Accordingly, submultiple frequency signals Q'₂-Q'₇ outputted from respective latch positions of the latch circuit 354are a square wave signal with a duty factor of 50%. The frequencies ofthe signals Q'₃, Q'₄, Q'₅, Q'₆ and Q'₇ are respectively 1/2, 1/4, 1/8,1/16 and 1/32 that of the signal Q'₂ having the highest frequency.Alternatively stated, the submultiple frequency signals Q'₂ -Q'₇ are inan octave relationship relative to each other.

The square wave submultiple frequency signals Q'₂ -Q'₇ outputted by thelatch circuit 354 are applied to a gating circuit 355. When the level ofthe submultiple frequency signals Q'₂ -Q'₇ is "0", field-effecttransistors 362 through 367 are turned on through inverters 356-361 toapply the ground voltage 0 from a ground voltage line 374 to tone sourcesignal lines 368 through 373. When the level of the submultiplefrequency signals Q'₂ -Q'₇ is "1" field-effect transistors 375 through380 are turned on to apply an envelope voltage from a line 381 to thetone source signal lines 368 through 373. Accordingly, the submultiplefrequency signals Q'₂ -Q'₇ are gates in the gating circuit 355 inaccordance with the envelope voltage characteristic and thereafter areprovided on the tone source signal lines 368-373.

Envelope Control

The key-on signal "KO₁ ·EC+KO₂ ·EC" stored in the latch circuit 275through the line 339 (FIG. 11) becomes the same signal as the firstkey-on signal KO₁ when the envelope control signal EC is "0" and thesame signal as the second key-on signal KO₂ when the envelope controlsignal EC is "1".

When the envelope control signal EC is set at "0", the key-on signal"KO₁ ·EC+KO₂ ·EC" appearing on the output line 339' of the latch circuit275 is the same as the first key-on signal KO₁, i.e., "1" only while theassigned key is being depressed. A field-effect transistor 382 is turnedon by this signal "1" on the line 339' and a negative voltage of -5 Vcharged in a capacitor 385 through resistors 383 and 384. The voltageacross the capacitor 385 is supplied as the envelope voltage waveshapeto the transistors 375 through 380 via the line 381. The resistors 383and 384 function to provide the envelope voltage waveshape with anattack characteristic and have a relatively small resistance value. If amore abrupt attack shape is desired, the field-effect transistor 386 isturned on by an attack data AT and the resistor 384 is short-circuited.The attack data AT is continuously provided by a switching or the likeoperation. When the first key-on signal KO₁ falls to "0" upon release ofthe depressed key, the signal on the line 339' is turned to "0" and thetransistor 382 is turned off. This causes the voltage of -5 V across thecapacitor 385 to be discharged through a resistor 387. The resistor 387is of a larger resistance value than the resistors 383 and 384 andfunctions to provide the voltage waveshape on the line 381 with agradually attenuating decay characteristic.

When the envelope control signal EC is "1", the second key-on signal KO₂of an attack shape which assumes "1" only during about 10 ms after startof depression of the key appears on the line 339'. If, accordingly, thesecond key-on signal KO₂ for the depressed key is turned to "0", thetransistor 382 is turned off even while the key is still being depressedand the envelope voltage waveshape on the line 381 is attenuated. Inthis manner, an attack envelope of a short duration (about 10 ms) isobtained.

When the damper signal DU is "1", the signal KO₁ ·DU becomes "1" uponrelease of the key and is stored in the latch circuit 275 through theline 338 (FIG. 11). This causes a field effect transistor 388 to beturned on with resulting connection of a resistor 389 to the capacitor385, the resistor 389 being grounded at one terminal thereof. Thecapacitor 385 thereby is discharged through the resistors 387 and 389connected in parallel. Accordingly, the time constant is reduced and aprompt discharge is effected resulting in shortening of the decay timeof the envelope voltage shape on the line 381. For this reason, the tonedecays rapidly upon release of the key if the damper signal DU is "1".

Octave selection

The tone source signals having been gated and outputted through the tonesource signal lines 368 through 373 of the gating circuit 355 (i.e.submultiple frequency signals Q'₂ -Q'₇) are applied to an octaveselection circuit 390. In the octave selection circuit 390, tone sourcesignals (Q'₂ -Q'₇) of a desired octave range are selected within fouroctave ranges with respect to each of the 2 foot, 4 foot, 8 foot and 16foot systems in accordance with octave selection data OS₁, OS₂, OS₃ andOS₄ latched by the latch circuit 375. In the octave selection circuit390, field-effect transistor groups 290-2', 290-4', 290-8' and 290-16'are provided corresponding to the 2 foot, 4 foot, 8 foot and 16 footsystems. In accordance with single octave selection data which is "1"(one of the octave selection data OS₁ through OS₀), the field-effecttransistors of the respective footage systems are turned on one by one.It should be noted that a tone source signal corresponding to the dataOS₀ which is for the highest octave does not exist in the 2 foot system.Accordingly, an arrangement is made in the 2 foot system so that if thedata So is "1", the tone source signal Q'₂ which is for the samefrequency as in the case where the data OS₁ is "1" is selected.

Assume, for example, that the key for the note C₄ has been depressed inthe upper keyboard and this key has been assigned to the fourth channelcorresponding to the tone generator 243. As will be apparent from theTables 2 and 3, the octave selection data OS₁ only is "1" and the otherdata OS₂ through OS₀ is "0". The tone source signals (Q'₂ -Q'₇) of therespective footage corresponding to the note C₄ are selected in responseto the data OS₁.

The output of the octave selection circuit 390 is outputted from thetone generator 242 through source follower type field-effect transistorgroup 391. The outputs of a field-effect transistor 290-2' of the 2 footsystem in the octave selection circuit 390 are all provided on a line392 and outputted as a 2 foot system musical tones signal U2' throughthe field-effect transistor group 391. The tone source signal for thefourth octave range of the 4 foot system is outputted as a 4 foot systemfourth octave musical tone signal U4'4 through a line 393. The octaverange selected by the octave selection data OS₁ herein is referred to asthe first octave range, that selected by the data OS₂ as the secondoctave range, that selected by the data OS₃ as the third octave rangeand that selected by the data OS₀ as the fourth octave range.

The tone source signal for the third octave range of the 4 foot systemis outputted as a 4 foot system third octave musical tone signal U4'3from the octave selection circuit 390 through a line 394. The tonesource signal for the fourth octave range of the 8 foot system isoutputted as an 8 foot system fourth octave musical tone signal U8'4from the octave selection circuit 390 through a line 395. The tonesource signal for the 8 foot system third octave range is outputted asan 8 foot system third octave musical tone signal U8'3 from the octaveselection circuit 390 through a line 396. The tone source signals forthe fourth and third octave ranges of the 16 foot system are outputtedas a 16 foot system fourth octave musical tone signal U16'4 and a 16foot system third octave musical tone signal U16'3 respectively from theoctave selection circuit 390 through lines 397 and 399.

The tone source signals for the second and first octave ranges of the 4foot system are commonly provided on a line 398 and are outputted as a 4foot system low octave range musical tone signal U4'2. The tone sourcesignals for the first and second octave ranges of the 8 foot system arecommonly provided on a line 400 and are outputted as an 8 foot systemlow octave range musical tone signal U8'2. The tone source signals forthe first and second octave ranges of the 16 foot system likewise arecommonly provided on a line 401 and are outputted as a 16 foot systemlow octave range musical tone signal U16'2.

The musical tone signals U2' through U16'2 on the output lines 392-401of the octave selection circuit 390 are mixed with musical tone signalscorresponding to footage systems and octave ranges of the other tonegenerators 244 thrugh 249 (FIG. 10) via source follower typefield-effect transistor group 391 and thereafter are outputted from thedigital tone generator section 16. In the source follower type fieldeffect transistor group 391, p-channel-depletion type field-effecttransistors are employed. The other field-effect transistors used in thepresent embodiment are p-channel-enhancement type ones. Accordingly, themusical tone signals of a negative amplitude voltage outputted from theoctave selection circuit 390 via the lines 392 through 401 are deliveredfrom the field-effect transistor group 391 without being inverted inpolarity.

The reason for producing musical tone signals of respective footages foreach octave range is that with respect to the upper keyboard tones, thetone level is corrected for each octave in a post-stage circuit (notshown) of the digital tone generator section 16. For example, bycorrecting the tone level in such a manner that the tone level of highoctave taones will become relatively large and that of low octave toneswill become relatively small, the post-stage circuit effects a controlfor accoustically balancing the tone levels of the high octave tones andthe low octave tones. For this purpose, the musical tones of therespective footages (U2', U4', U8' and U16') are divided into the fourthoctave range (U4'4, U8'4 and U16'4), the third octave range (U4'3, U8'3and U16'3) and the low octave range (U4'2, U8'2 and U16'2) for the tonelevel correction in the post-stage circuit.

A circuit 402 is provided between the octave selection circuit 390 andthe field-effect transistor group 391 for making the potential of theoutput lines 393 through 401 of tone source signals not selected by theoctave selection data OS₁ -OS₀ ground potential. More specifically, whenthe octave selection data OS₁ -OS₀ is "0", corresponding field-effecttransistors in the circuit 402 are turned on through an inverter 403 or404 or a NOR gate 405 and lines among the lines 393 through 401corresponding to the data OS₁ -OS₀ which is "0" are connected to theground line 374 through the field-effect transistors which are on. Asfor the line 392, tone source signals of all octave ranges of the 2 footsystem are applied to the line 392 and tone source signals selected byany of the data OS₁ -OS₀ appear on the line 392 so that the abovedescribed arrangement provided for the lines 393 through 401 isunnecessary.

Lower keyboard tone generator

As an example of the lower keyboard tone generator, the tone generator250 for the ninth channel is illustrated in detail in FIG. 16. The othertone generator 251 through 256 are of the same construction.

With reference to FIG. 16, a note selection circuit 406 is of the sameconstruction as the note selection circuit 346 shown in FIG. 15,functioning to select submultiple frequency data on the lines 342-1through 342-12. It is possible to employ the same gating circuit andoctave selection circuit as are shown in FIG. 15, but in the presentexample an octave selection circuit is made different from that of FIG.15 by utilizing the fact that the submultiple frequency data Q₂ -Q₇ isserially produced.

A 7-stage shift register 407, a NOR gate 408, a set-reset type flip-flop409, a delay flip-flop 410 and an AND gate 411 to which the submultiplefrequency data Q₂ -Q₇ corresponding to the notes of the tones assignedto the respective channels and selected by the note selection circuit406 is applied operate substantially in the same manner as the shiftregister 348, NOR gate 349, flip-flop 351, delay flip-flop 352 and ANDgate 353 shown in FIG. 15. A latch circuit 412 which stores in parallelthe submultiple frequency data Q₂ -Q₇ received by the shift register 407is of a 3 bit, different from the latch circuit 354 shown in FIG. 15.Latch positions of the latch circuit 412 correspond respectively to the2 foot system (L2'), 4 foot system (L4') and 8 foot system (L8').

The outputs of the first, second and third stages of the shift register407 are loaded in the latch circuit 412. The octave selection data OS₀-OS₁ stored in the latch circuit 282 is applied to AND gates 413-416 anda single AND gate (one of the AND gates 413 through 416) correspondingto the octave range of the note assigned to the specified channel isenabled. These AND gates 413 through 416 receive at the other inputthereof the outputs of the fourth through seventh stages of the shiftregister 407.

When the timing pulse TP (FIG. 14) preceding the submultiple frequencydata Q₂ -Q₇ has entered the first stage of the shift register 407, theNOR gate 408 is enabled to set the flip-flop 409. When this timing pulseTP has entered the fourth through seventh stages, the AND gate 413through 416 are enabled to reset the flip-flop 409 through the OR gate464 and also apply a strobe pulse to the latch circuit 412 through theAND gate 411. As shown in FIG. 14, in the submultiple frequency datatrain D₁, D₂ . . . , data Q₂, Q₃, . . . Q₇ is arranged in the order ofmagnitude of frequency. If, accordingly, the AND gate 413 is enabled forexample by the data OS₀ corresponding to the fourth octave, thesubmultiple frequency data present in the first through third stages ofthe shift register 407 is Q₄, Q₃ and Q₂ when the timing pulse TP hasentered the fourth stage of the shift register 407, these data beingloaded into the latch circuit 412. If the octave selection data OS₃ is"0", the AND gate 414 is enabled to load the submultiple frequency dataQ₅, Q₄ and Q₃ in the latch circuit 412.

A square wave signal appearing on an output line 417 of the latchcircuit 412 latching the submultiple frequency data of the third stageof the shift register 407 corresponds to the 2 foot system tone sourcesignal L2, a square wave signal appearing on an output line 418 of thelatch circuit 412 latching the submultiple frequency data of the secondbit corresponds to the 4 foot system tone source signal L4', a squarewave signal appearing on an output line 419 of the latch circuit 412latching the submultiple frequency data of the first bit corresponds tothe 8 foot system tone source signal L8'. The octave range of the squarewave signals appearing on the lines 417 through 419 differs dependingupon the state of the octave selection data OS₁ -OS₀. The relationshipbetween the octave selection data OS₀ -OS₁, the submultiple frequencydata Q₂ -Q₇ and the ratio of frequencies thereof is shown in thefollowing Table 7. In Table 7, the frequency of the tone source squarewave signal obtained in accordance with the submultiple frequency dataQ₂ is taken as 1.

                  TABLE 7                                                         ______________________________________                                        Latch                                                                         output     Ocatave selection data                                             line       OS.sub.0                                                                             OS.sub.3   OS.sub.2                                                                            OS.sub.1                                   ______________________________________                                        417        Q.sub.2                                                                              Q.sub.3    Q.sub.4                                                                             Q.sub.5                                    (L.sub.2 2')                                                                             (1)    (1/2)      (1/4) (1/2)                                      418        Q.sub.3                                                                              Q.sub.4    Q.sub.5                                                                             Q.sub.6                                    (L4')      (1/2)  (1/4)      (1/2) (1/16)                                     419        Q.sub.4                                                                              Q.sub.5    Q.sub.6                                                                             Q.sub.7                                    (L8')      (1/4)  (1/2)      (1/16)                                                                              (1/32)                                     ______________________________________                                    

Gating of the lower keyboard tones

The first key-on signal KO₁ latched in the latch circuit 282 via theline 326 (FIG. 11) is applied to AND gates 422 through 429 of gatingcircuits 420 and 421 Accordingly, the gating circuits 420 and 421operate only when the key is being depressed.

The tone source signal provided on the lines 417 through 419 from thelatch circuit 412 is a square wave signal with a duty factor of 50%.This tone source signal on the lines 417 through 419 is gate-controlledby the first gating circuit 420 in accordance with the first key-onsignal KO₁ and thereafter is outputted through lines 430, 431 and 432.If the level of the tone source square wave signal is "0", the groundpotential on a ground potential line 433 is delivered on the lines 430through 432 whereas if the level of the tone source square wave signalis "1", a negative voltage -5 V on a line 434 is delivered on the lines430 through 432. Since the tone source signals are gate-controlled inaccordance with the first key-on signal KO₁, the tone source signalsL2', L4' and L8' of he respective footage systems are provided with anamplitude envelope of a direct keying type which is abrupt in both riseand fall.

Tone level correction for each octave range

The tone source signals on the lines 430 through 432 are applied to atone level correction circuit 435 for correction in the tone levelaccording to the octave range thereof. In the above described upperkeyboard tone generator 243 through 249, the musical tone signals U2'through U16'2 are outputted so that the tone level is corrected in apost-stage circuit and not in the tones generators. In the lowerkeyboard tone generators 250 through 256, the tone source signals of therespective footages on the lines 430 through 432 are corrected in thetone level with respect to each octave and thereafter are outputted aslower keyboard musical tone signals L2', L4' and L8' of the respectivefootage systems.

The octave range of the tone source signals provided on the lines 430through 432 is designated by the octave selection data OS₁ -OS₀ latchedby the latch circuit 282. Accordingly, reistance value of the tone levelcorrection circuit 435 is changed in accordance with the contents of theoctave selection data OS₁ -OS₀. The tone level correction is appliedonly to the musical tone signals of the 4 foot and 8 foot systems on thelines 431 and 432. The musical tone signal of the 2 foot system on theline 430 is generally in a high octave range so that the levelcorrection for each octave range is not effected.

If the musical tone signals on the lines 431 and 432 are ones of a lowoctave range selected by the octave selection data OS₁ or OS₂, resistorsR₁, R₂, R₁₃ and R₁₁, R₁₂, R₁₃ provided in the series in the lines 431and 432 are respectively connected in series resulting in maximum amountof attenuation of the musical tone. Accordingly, the tone level of themusical tone signal in the low octave range becomes relatively small. Ifthe musical tone signals on the lines 431 and 432 are ones of the thirdoctave range selected by the octave selection data OS₃, the field-effecttransistors 436 and 437 are turned on by the data OS₃ outputted from thelatch circuit 282 and the resistors R₁ and R₁₁ are therebyshort-circuited. Accordingly, the musical tone signals are attenuated bythe serially connected resistors R₂, R₃ and R₁₂, R₁₃ so that the tonelevel of the musical tone signal of the third octave range becomesrelatively large as compared with the tone level of the musical tonesignals in the low octave range. If the musical tone signals on thelines 431 and 432 are ones of the highest octave range (i.e. the fourthoctave), transistors 438 and 439 are turned on by the data OS₀ outputtedfrom the latch circuit 282 resulting in short-circuiting of theresistors R₁, R₂ and R₁₁, R₁₂. Accordingly, the musical tone signals ofthe highest octave range appearing on the lines 431 and 432 areattenuated only by the resistors R₃ and R₁₃ so that the tone levelthereof becomes relatively the largest of all of the musical tonesignals.

Gating of automatic chord tones

Tone source signals for the automatic chord performance are obtained onthe basis of the lower keyboard tone source square wave signals of therespective footages provided on the lines 417 through 419 from the latchcircuit 412. This is because the automatic chord tones are obtained bysimultaneously producing tones of the keys being depressed in the lowerkeyboard at a timing of the automatic chord tone key-on signal KO₃.

Square wave signals of the 4 foot and 8 foot systems with a duty factorof 50% are applied from the lines 418 and 419 to an AND gate 440 toobtain a square wave signal (A8) of the 8 foot system with a duty factorof 1/4. Similarly, square wave signals of the 2 foot and 4 foot systemswith a duty factor of 50% are applied from the lines 417 and 418 an ANDgate 441 to obtain a square wave signal (A4') with a duty factor of 1/4.The square wave signals of the respective footage systems appearing onthe lines 410 through 419 are synchronized in their phase with oneanother. Accordingly, the square wave signals with a duty factor ofexactly 1/4 are obtained from the AND gates 440 and 441. These squarewave signals of the 4 foot and 8 foot systems produced by the AND gates440 and 441 are inputted to the second gating circuit 421 as theautomatic chord tone source signals.

The second gating circuit 421 receives a signal from the automatic chordtone envelope control section 330. Being controlled by this controlsection 330, the second gating circuit 421 does not effect a gatingoperation if the automatic bass chord performance is not made. Morespecifically, if the automatic bass chord performance is not made, theautomatic bass chord selection signal ABC latched by the latch circuit331 is "0" and the automatic chord key-on signal KO₃ is "0" (the signalKO₃ is not produced unless the automatic bass chord is selected).Accordingly, the output of a NOR gate 442 is "1" and a field-effecttransistor 443 is always in conduction. This causes the ground potentialon a ground potential line 433 to be delivered on a line 444 so that thegating circuit 421 always outputs the ground potential. Accordingly, themusical tone signals A4' and A8' for the automatic chord are notproduced.

If the automatic base chord performance is selected, the signal ABC isturned to "1" so that the output of a NOR gate 442 is turned to "1" anda field-effect transistor 443 is always maintained in an off state.Simultaneously, a field-effect transistor 445 is turned on insynchronization with the automatic chord tone key-on signal KO₃ latchedby the latch circuit 331. As the transistor 445 is turned on, thenegative voltage -5 V on the line 434 is charged in a capacitor 446. Asthe transistor 445 is turned off by falling of the key-on signal KO₃,the capacitor 446 is discharged through a resistor 447. Accordingly, avoltage waveform of the capacitor 446 which is charged and discharged inaccordance with generation and extinguishment of the key-on signal KO₃appears on the line 444. The pulse width of the key-on signal KO₃ is ashort one of about 5 ms. If, accordingly, a relatively large value ofresistance of a resistor 447 is selected, a percussion type envelopevoltage waveform with a long decay time is obtained on the line 444.

In the gating circuit 421, a gating control is effected in accordancewith the envelope voltage waveform on the line 444. When the level ofthe square wave signal outputted from the AND gates 440 and 441 is "0",the ground potential on the ground potential line 433 is delivered onoutput lines 448 and 449, whereas when the level of the square wavesignal is "L", the envelope voltage waveform on the line 444 isdelivered on the output lines 448 and 449. Accordingly, the tone sourcesquare wave signals of the 8 foot and 4 foot systems amplitude-modulatedby the envelope voltage waveform provided on the line 444 are deliveredon the line 444 are delivered on the lines 448 and 449. The tone sourcesignals on the lines 448 and 449 are outputted as an 8 foot systemautomatic chord tone signal A8' and a 4 foot system automatic chord tonesignal A4' are source-follower type field-effect transistors 450 and451.

If a rhythm of slow rock is selected, a field-effect transistor 452 isturned on by a slow rock selection signal SR latched by the latchcircuit 331 through the line 326 thereby causing a resistor 453 which isgrounded at one terminal thereof to be connected to the line 444.Accordingly, a parallel circuit of the resistors 447 and 453 is formedwith a result that time constant in discharging of the capacitor 446 isshortened. Consequently, if the slow rock rhythm is selected, the decaytime of the amplitude envelope of the automatic chord tone is shortened.

The above described gating control for the automatic chord tones issimultaneously effected with respect to all of the lower keyboard tonegenerators 250 through 256.

Pedal kayboard tone generator

FIG. 17 shows an example of the pedal keyboard tone generator 242. Thetone generator 242 is a digital type tone generator including a maximumlength counter 454, a coincidence detection circuit 455 and read-onlymemory 456. A clock pulse φp used for driving the maximum length counter454 is oscillated from a source separate from the source of the masterclock pulse φ_(M) used in the submultiple frequency signal generator 341(FIGS. 10 and 13). Accordingly, the frequency-modulation of the masterclock pulse φ_(p) for applying vibrato to the upper and lower keyboardtones in no way affects the clock pulse φ_(p) and vibrato is not appliedto the pedal keyboard tones.

In accordance with contents of the note selection data n₁ -n₆ and N₄ *latched by the latch circuit 290, the read-only memory 456 reads out10-bit digital data corresponding to the note of the pedal keyboard toneassigned to the pedal keyboard channel (i.e. the first channel). Thecoincidence circuit 455 composed of an exclusive OR gate comparescontents of the maximum length counter 454 with contents of the digitaldata read from the read-only memory 456 and produces a coincidencedetection pulse CON whenever they coincide with each other. Thiscoincidence detection pulse CON sets all bits of the contents of themaximum length counter 454 to "1". The pulse CON corresponds to a signalof the highest frequency of the note assigned to the specified channel.The counter 458 divides this signal in frequency to form tone sourcesignals of the respective octave ranges.

The tone source signals (square wave signals with a duty factor of 50%)outputted in parallel from the counter 458 are applied to an octaveselection circuit 459 in which tone source signals of required octavesare selected in accordance with the octave selection data OS₀, OS₁ andOS₂. With respect to the pedal keyboard, the data OS₃ is not used (SeeTables 3 and 4) so that the data OS₃ need not be latched. In the pedalkeyboard, the data OS₀ represents the lowest octave range (See Tables 3and 4).

The outputs of the octave selection circuit 459 is applied to AND gates460 and 461 depending upon the footage system. The AND gate 460 is acircuit which produces a 16 foot system pedal keyboard tone sourcesignal (P16') in the form of a square wave signal with a duty factor of1/4. The AND gate 461 is a circuit which produces an 8 foot system pedalkeyboard tone source signal (P8') in the form of a square wave signalwith a duty factor of 1/4. In other words, the octave selection circuit459 selects tone source signal (square wave signals with a duty factorof 50%) within three octave ranges in accordance with the octaveselection data OS₀, OS₁ or OS₂. Among the three tone source signals, theadjacent two tone source signals (i.e., submultiple frequency signalswhose frequencies are in a relation of 1:2) are inputted to the ANDgates 460 and 461. As a result, a 16 foot system square wave signal witha duty factor of 1/4 is provided by the AND gate 460 and an 8 footsystem square wave signal with a duty factor of 1/4 which is one octavehigher is provided by the AND gate 461.

The tone source signals outputted by the respective AND gates 460 and461 are applied to a gating circuit 462 in which these signals aregate-controlled in accordance with the first key-on signal KO₁ latchedby the latching circuit 274. In this manner, the 8 foot system and 16foot system pedal keyboard musical tone signals P8' and P16' areproduced.

In a case where the digital tone generator 16 is made in the form of anintegrated circuit, capacitors and discharging resistors in the gatingcircuit are provided outside of the integrated circuit as externalcomponent parts.

What is claimed is:
 1. A keyboard electronic musical instrument having aspecified number of tone production channels connected by a number ofoutput lines, comprising:a tone production assignment circuit forassigning production of a tone selected by depression of a key to one ofsaid channels and generating key information representing the note nameof the assigned tone and key-on information representing depression orrelease of the key with respect to each channel to which tone productionhas been assigned, said key information and said key-on information foreach channel together having a certain total number of bits; datadividing means, connected to said assignment circuit and having paralleloutput lines of a number which is smaller than said certain total numberof bits of the key information and the key-on information for eachchannel, for dividing the key information and the key-on information ofthe tone assigned to the particular channel into groups of data, eachgroup having a number of bits matching the number of said output lines;data multiplexing means, cooperatively connected to said data dividingmeans, for time division multiplexing said groups of divided data bydelivering each group of data on said output lines in parallel dataformat, said groups being delivered sequentially in time divisionmultiplexed order; and a tone generator for generating the tone assignedto each channel in accordance with the multiplexed data.
 2. Anelectronic musical instrument as defined in claim 1 wherein said datamultiplexing means comprises means for periodically inserting datarepresenting a reference timing in said output lines.
 3. An electronicmusical instrument as defined in claim 2 wherein said data multiplexingmeans further comprises means for inserting control information usedcommonly throughout all of the channels or used for only a specifiedchannel in any one or more of the output lines at a suitable timing whencomponent data of the key information or the key-on information is notprovided on said one or more of the output lines.
 4. An electronicmusical instrument as defined in claim 1 wherein said data dividingmeans comprises:first through N-th selection means for dividing saidtotal number of bits of the key information and the key-on informationinto N groups (where N represents an integer of 2 or a larger number)with respect to each of the channels and for sequentially selecting eachof the divided groups of data with a time delay; and wherein said datamultiplexing means comprises: gating means for selecting one or morecontrol information used commonly throughout all of the channels or foronly a specified channel at a predetermined timing; OR gate groupshaving a specified number of parallel output lines for combining theoutputs of said first through N-th selection means and said gatingmeans; control means for generating first through N-th pulsessequentially and repeatedly with a delay of a predetermined time periodfor controlling the timing of sequential selection by said first throughN-th selection means; timing pulse generation means for generating atiming pulse which controls the timing of selection by said gatingmeans; and reference data insertion means for inputting a control pulsegenerated at a certain reference time within each repetitive cycle inwhich information of all of the channels is multiplexed, and forsupplying a unique group of data representing the reference timing tosaid OR gate groups in response to said input control pulse.
 5. Anelectronic musical instrument as defined in claim 4 which furthercomprises multiplexed data distribution means which receives themultiplexed data provided by said data multiplexing means through saidoutput lines and distributes each of the multiplexed data to each ofseparate tone generators in accordance with the channel of themultiplexed data.
 6. An electrical musical instrument as defined inclaim 5 wherein said multiplexed data distribution means comprises:meansfor detecting the data representing the reference timing from among themultiplexed data supplied by said data multiplexing means for generatinga reference pulse in response to the detection; shift means forsuccessively shifting the reference pulse; and latch means forsuccessively latching the multiplexed data provided by said datamultiplexing means in accordance with the reference pulse successivelyshifted in said shift means thereby to distribute the key informationand the key-on information contained in the multiplexed data to therespective channels. .Iadd.
 7. A polyphonic keyboard electronic musicalinstrument having a specified number of tone production channels,comprising: key information generating means for generating keyinformation relating to depressed ones among keys in a keyboard, channelassignment means for assigning said key informations to available onesof the specified number of tone production channels, multiplexing meansfor time division multiplexing said assigned key informations bydelivering each key information in parallel data format, said keyinformations being delivered sequentially in time division multiplexedorder; tone generating means having the same number of tone generatorsas said specified number of tone production channels, each of said tonegenerators corresponding to a respective one of said tone productionchannels, and demultiplexing means connected between said multiplexingmeans and said tone generating means for demultiplexing said deliveredkey informations and for supplying each demultiplexed key information tothe tone generator corresponding to the tone production channel to whichsaid delivered key information is assigned, so that said tone generatorsrespectively generate tone signals in accordance with the respectivesupplied key information. .Iaddend. .Iadd.
 8. A polyphonic electronicmusical instrument comprising: keyboard means having a plurality ofkeys, key information generating means for generating key informationrelating to depressed ones among said keys, channel assignment means forassigning said key information to available ones of a specified numberof tone production channels, envelope information generating means forgenerating envelope information serving to determine an envelopecharacteristic of a tone, said envelope information being used commonlythroughout all of said tone production channels, multiplexing meansconnected to said channel assignment means and said envelope informationgenerating means for transmitting said key information and said envelopeinformation over output lines using a predetermined number of timeslots, each of said key information being allotted to a predeterminedtime slot in accordance with the assigned tone production channel of thekey information and the envelope information being allotted to apredetermined time slot on one or more of said output lines in whichsaid key information is not provided, tone generating means having tonegenerators each of which corresponds to a respective one of the toneproduction channels, envelope imparting means having envelope impartingcircuits each of which is connected to a respective one of said tonegenerators; and demultiplexing means connected to said output lines forsupplying said transmitted key information to the tone generatorscorresponding to said tone production channels to which said transmittedkey information is assigned respectively and for supplying saidtransmitted envelope information to all of said envelope impartingcircuits, said tone generators generating tone signals in accordancewith said supplied key information respectively and said envelopeimparting circuits imparting the envelope characteristic to thecorresponding tone signals. .Iaddend. .Iadd.
 9. In a keyboard polyphonicelectronic musical instrument of the type having plural tone generatorchannels, the number of such channels being considerably fewer than thetotal number of keys, the improvement comprising: memory means storing achannel assignment table containing for each assigned channel a key codeand associated key depression state data for the selected key which isassigned to that channel, data transmission lines, time divisionmultiplex means for repetitively, consecutively transmitting thecontained key codes and associated key depression state data via saiddata transmission lines during corresponding intervals in each timedivision multiplex cycle, and demultiplexer means, connected to saiddata transmission lines and receiving said time division multiplex keycodes and data, for demultiplexing the same and supplying to each tonegenerator channel only the demultiplexed key code and associated keydepression state data for the selected key assigned to that channel..Iaddend. .Iadd.
 10. An electronic musical instrument according to claim9 further comprising: envelope information generating means forproducing envelope ascertaining information for common usage by all ofsaid tone generator channels, said multiplexer means including circuitryfor transmitting said envelope ascertaining information from saidenvelope information generating means onto said data transmission linesas part of each time division multiplex cycle, and an envelope impartingcircuit in each tone generator channel, each envelope imparting circuitutilizing said transmitted common envelope ascertaining information andthe key depression state data for the corresponding channel to impartthe requisite envelope to the tone generated in that channel..Iaddend..Iadd.
 11. An electronic musical instrument according to claim10 wherein said multiplexer means gates said envelope ascertaininginformation onto said data transmission lines at the beginning of eachtime division multiplex cycle. .Iaddend. .Iadd.
 12. A keyboardelectronic musical instrument having a specified number of toneproduction channels connected by a number of output lines, comprising: atone production assignment circuit for assigning production of a toneselected by depression of a key to one of said channels and generatingkey information representing the note name of the assigned tone andkey-on information representing depression or release of the key withrespect to each channel to which tone production has been assigned, saidkey information and said key-on information for each channel togetherhaving a certain total number of bits; a number of parallel outputtransmission lines; data multiplexing means for time divisionmultiplexing said key information and key-on information by deliveringthe same on said output transmission lines in parallel data format, saidinformation being delivered sequentially in time division multiplexedorder, a tone generator for generating the tone assigned to each channelin accordance with the multiplexed information, and means for insertingenvelope control information used commonly throughout all of thechannels or used for only a specified channel in any one or more of theoutput transmission lines at a suitable timing when component data ofthe key information or the key-on information is not provided on saidone or more of the output transmission lines. .Iaddend. .Iadd.
 13. In akeyboard electronic musical instrument of the type having a small numberof tone generator channels, for which channels key code and keydepression state data are supplied in time division multiplex format,the improvement comprising: assignment memory means containing a channelassignment table in which there is a data entry position for each tonegenerator channel, first means for ascertaining by comparison with priorentered data in said table whether a key code for a selected key isalready entered in said table and if not, for entering the key code andassociated key depression state data for that selected key into anavailable data entry position of said table, second means for readingout all of the entered key codes and associated key depression statedata from said channel assignment table in a certain order and incertain delivery time zones for time division multiplex transmission tosaid tone generator channels, and timing control means, cooperativelyconnected to said first and second means, for establishing a timing andorder for key code and data entry into said table by said first means,and for establishing a different timing and order for readout andtransmission of key codes and data from said table by said second means..Iaddend.